110 lines
4.9 KiB
C
110 lines
4.9 KiB
C
// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ___FW_DMA_H___
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#define ___FW_DMA_H___
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#include "fw_conf.h"
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#include "fw_types.h"
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typedef enum
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{
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DMA_BusPriority_Lowest = 0x00,
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DMA_BusPriority_Low = 0x01,
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DMA_BusPriority_High = 0x02,
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DMA_BusPriority_Highest = 0x03,
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} DMA_BusPriority_t;
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/**************************************************************************** /
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* DMA M2M
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*/
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#define DMA_M2M_SetSrcAddrIncrement(__STATE__) SFRX_ASSIGN(DMA_M2M_CFG, 5, __STATE__)
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#define DMA_M2M_SetDstAddrIncrement(__STATE__) SFRX_ASSIGN(DMA_M2M_CFG, 4, __STATE__)
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#define DMA_M2M_SetBusPriority(__PRI__) SFRX_ASSIGN2BIT(DMA_M2M_CFG, 0, __PRI__)
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#define DMA_M2M_SetEnabled(__STATE__) SFRX_ASSIGN(DMA_M2M_CR, 7, __STATE__)
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#define DMA_M2M_Start() SFRX_SET(DMA_M2M_CR, 6)
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#define DMA_M2M_ClearInterrupt() SFRX_RESET(DMA_M2M_STA, 0)
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/**
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* Transfer size = __LEN__ + 1
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*/
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#define DMA_M2M_SetTxLength(__LEN__) do{SFRX_ON(); DMA_M2M_AMT = (__LEN__); SFRX_OFF();}while(0)
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#define DMA_M2M_SetSrcAddr(__16BIT_ADDR__) do{ \
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SFRX_ON(); \
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(DMA_M2M_TXAH = ((__16BIT_ADDR__) >> 8)); \
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(DMA_M2M_TXAL = ((__16BIT_ADDR__) & 0xFF)); \
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SFRX_OFF(); \
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} while(0)
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#define DMA_M2M_SetDstAddr(__16BIT_ADDR__) do{ \
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SFRX_ON(); \
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(DMA_M2M_RXAH = ((__16BIT_ADDR__) >> 8)); \
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(DMA_M2M_RXAL = ((__16BIT_ADDR__) & 0xFF)); \
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SFRX_OFF(); \
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} while(0)
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/**************************************************************************** /
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* DMA ADC
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*/
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typedef enum
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{
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DMA_ADC_ConvTimes_1 = 0x00,
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DMA_ADC_ConvTimes_2 = 0x08,
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DMA_ADC_ConvTimes_4 = 0x09,
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DMA_ADC_ConvTimes_8 = 0x0a,
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DMA_ADC_ConvTimes_16 = 0x0b,
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DMA_ADC_ConvTimes_32 = 0x0c,
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DMA_ADC_ConvTimes_64 = 0x0d,
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DMA_ADC_ConvTimes_128 = 0x0e,
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DMA_ADC_ConvTimes_256 = 0x0f,
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} DMA_ADC_ConvTimes_t;
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#define DMA_ADC_SetBusPriority(__PRI__) SFRX_ASSIGN2BIT(DMA_ADC_CFG, 0, __PRI__)
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#define DMA_ADC_SetEnabled(__STATE__) SFRX_ASSIGN(DMA_ADC_CR, 7, __STATE__)
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#define DMA_ADC_Start() SFRX_SET(DMA_ADC_CR, 6)
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#define DMA_ADC_ClearInterrupt() SFRX_RESET(DMA_ADC_STA, 0)
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#define DMA_ADC_SetDstAddr(__16BIT_ADDR__) do{ \
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SFRX_ON(); \
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(DMA_ADC_RXAH = ((__16BIT_ADDR__) >> 8)); \
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(DMA_ADC_RXAL = ((__16BIT_ADDR__) & 0xFF)); \
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SFRX_OFF(); \
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} while(0)
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#define DMA_ADC_SetConvTimes(__TIMES__) do{ \
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SFRX_ON(); \
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DMA_ADC_CFG2 = DMA_ADC_CFG2 & ~(0x0F) | ((__TIMES__) & 0x0F); \
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SFRX_OFF(); \
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} while(0)
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/**
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* auto-scann channels. scanning always starts from lower number channels.
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*
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* @param __16BIT_CHANNEL__: from high to low each bit stands for one ADC channel,
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* start from ADC15 to ADC0, e.g. 0x11 means ADC8 and ADC0
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*/
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#define DMA_ADC_EnableChannels(__16BIT_CHANNEL__) do{ \
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SFRX_ON(); \
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DMA_ADC_CHSW0 = (__CHANNEL__ >> 8) & 0xFF; \
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DMA_ADC_CHSW1 = __CHANNEL__ & 0xFF; \
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SFRX_OFF(); \
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} while(0)
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/**************************************************************************** /
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* DMA SPI
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*/
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#endif
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