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feat: dma for m2m and adc

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This commit is contained in:
IOsetting 2022-01-10 20:19:12 +08:00
parent c786635e33
commit 83283f7da4
7 changed files with 261 additions and 14 deletions
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2
include/fw_adc.h
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@ -49,7 +49,7 @@
* 1110 N/A P3.6/ADC14 P0.6/ADC14 P0.6/ADC14 P0.6/ADC14 N/A P3.6/ADC14 P0.6/ADC14
* 1111 Internal 1.19V voltage reference
*/
#define ADC_SetChannel(__CHANNEL__) (ADC_CONTR = ADC_CONTR & ~0x0F | ((__CHANNEL__) << 0))
#define ADC_SetChannel(__CHANNEL__) (ADC_CONTR = ADC_CONTR & ~0x0F | ((__CHANNEL__ & 0x0F) << 0))
/**
* 10-bit in [ADC_RES,ADC_RESL]: STC8H1K28,STC8H1K08

109
include/fw_dma.h Normal file
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@ -0,0 +1,109 @@
// Copyright 2021 IOsetting <iosetting(at)outlook.com>
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ___FW_DMA_H___
#define ___FW_DMA_H___
#include "fw_conf.h"
#include "fw_types.h"
typedef enum
{
DMA_BusPriority_Lowest = 0x00,
DMA_BusPriority_Low = 0x01,
DMA_BusPriority_High = 0x02,
DMA_BusPriority_Highest = 0x03,
} DMA_BusPriority_t;
/**************************************************************************** /
* DMA M2M
*/
#define DMA_M2M_SetSrcAddrIncrement(__STATE__) SFRX_ASSIGN(DMA_M2M_CFG, 5, __STATE__)
#define DMA_M2M_SetDstAddrIncrement(__STATE__) SFRX_ASSIGN(DMA_M2M_CFG, 4, __STATE__)
#define DMA_M2M_SetBusPriority(__PRI__) SFRX_ASSIGN2BIT(DMA_M2M_CFG, 0, __PRI__)
#define DMA_M2M_SetEnabled(__STATE__) SFRX_ASSIGN(DMA_M2M_CR, 7, __STATE__)
#define DMA_M2M_Start() SFRX_SET(DMA_M2M_CR, 6)
#define DMA_M2M_ClearInterrupt() SFRX_RESET(DMA_M2M_STA, 0)
/**
* Transfer size = __LEN__ + 1
*/
#define DMA_M2M_SetTxLength(__LEN__) do{SFRX_ON(); DMA_M2M_AMT = (__LEN__); SFRX_OFF();}while(0)
#define DMA_M2M_SetSrcAddr(__16BIT_ADDR__) do{ \
SFRX_ON(); \
(DMA_M2M_TXAH = ((__16BIT_ADDR__) >> 8)); \
(DMA_M2M_TXAL = ((__16BIT_ADDR__) & 0xFF)); \
SFRX_OFF(); \
} while(0)
#define DMA_M2M_SetDstAddr(__16BIT_ADDR__) do{ \
SFRX_ON(); \
(DMA_M2M_RXAH = ((__16BIT_ADDR__) >> 8)); \
(DMA_M2M_RXAL = ((__16BIT_ADDR__) & 0xFF)); \
SFRX_OFF(); \
} while(0)
/**************************************************************************** /
* DMA ADC
*/
typedef enum
{
DMA_ADC_ConvTimes_1 = 0x00,
DMA_ADC_ConvTimes_2 = 0x08,
DMA_ADC_ConvTimes_4 = 0x09,
DMA_ADC_ConvTimes_8 = 0x0a,
DMA_ADC_ConvTimes_16 = 0x0b,
DMA_ADC_ConvTimes_32 = 0x0c,
DMA_ADC_ConvTimes_64 = 0x0d,
DMA_ADC_ConvTimes_128 = 0x0e,
DMA_ADC_ConvTimes_256 = 0x0f,
} DMA_ADC_ConvTimes_t;
#define DMA_ADC_SetBusPriority(__PRI__) SFRX_ASSIGN2BIT(DMA_ADC_CFG, 0, __PRI__)
#define DMA_ADC_SetEnabled(__STATE__) SFRX_ASSIGN(DMA_ADC_CR, 7, __STATE__)
#define DMA_ADC_Start() SFRX_SET(DMA_ADC_CR, 6)
#define DMA_ADC_ClearInterrupt() SFRX_RESET(DMA_ADC_STA, 0)
#define DMA_ADC_SetDstAddr(__16BIT_ADDR__) do{ \
SFRX_ON(); \
(DMA_ADC_RXAH = ((__16BIT_ADDR__) >> 8)); \
(DMA_ADC_RXAL = ((__16BIT_ADDR__) & 0xFF)); \
SFRX_OFF(); \
} while(0)
#define DMA_ADC_SetConvTimes(__TIMES__) do{ \
SFRX_ON(); \
DMA_ADC_CFG2 = DMA_ADC_CFG2 & ~(0x0F) | ((__TIMES__) & 0x0F); \
SFRX_OFF(); \
} while(0)
/**
* auto-scann channels. scanning always starts from lower number channels.
*
* @param __16BIT_CHANNEL__: from high to low each bit stands for one ADC channel,
* start from ADC15 to ADC0, e.g. 0x11 means ADC8 and ADC0
*/
#define DMA_ADC_EnableChannels(__16BIT_CHANNEL__) do{ \
SFRX_ON(); \
DMA_ADC_CHSW0 = (__CHANNEL__ >> 8) & 0xFF; \
DMA_ADC_CHSW1 = __CHANNEL__ & 0xFF; \
SFRX_OFF(); \
} while(0)
/**************************************************************************** /
* DMA SPI
*/
#endif

26
include/fw_exti.h
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@ -144,6 +144,19 @@ typedef enum
#define EXTI_RTC_SetSecondDiv8IntState(__STATE__) SFRX_ASSIGN(RTCIEN, 1, __STATE__)
#define EXTI_RTC_SetSecondDiv32IntState(__STATE__) SFRX_ASSIGN(RTCIEN, 0, __STATE__)
#define EXTI_DMA_M2M_SetIntState(__STATE__) SFRX_ASSIGN(DMA_M2M_CFG, 7, __STATE__)
#define EXTI_DMA_ADC_SetIntState(__STATE__) SFRX_ASSIGN(DMA_ADC_CFG, 7, __STATE__)
#define EXTI_DMA_SPI_SetIntState(__STATE__) SFRX_ASSIGN(DMA_SPI_CFG, 7, __STATE__)
#define EXTI_DMA_UART1T_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR1T_CFG, 7, __STATE__)
#define EXTI_DMA_UART1R_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR1R_CFG, 7, __STATE__)
#define EXTI_DMA_UART2T_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR2T_CFG, 7, __STATE__)
#define EXTI_DMA_UART2R_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR2R_CFG, 7, __STATE__)
#define EXTI_DMA_UART3T_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR3T_CFG, 7, __STATE__)
#define EXTI_DMA_UART3R_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR3R_CFG, 7, __STATE__)
#define EXTI_DMA_UART4T_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR4T_CFG, 7, __STATE__)
#define EXTI_DMA_UART4R_SetIntState(__STATE__) SFRX_ASSIGN(DMA_UR4R_CFG, 7, __STATE__)
#define EXTI_DMA_LCM_SetIntState(__STATE__) SFRX_ASSIGN(DMA_LCM_CFG, 7, __STATE__)
#define EXTI_INT_PWMA_Break_ON SFRX_SET(PWMA_IER, 7)
#define EXTI_INT_PWMA_Break_OFF SFRX_RESET(PWMA_IER, 7)
#define EXTI_INT_PWMA_Int_ON SFRX_SET(PWMA_IER, 6)
@ -205,6 +218,19 @@ typedef enum
#define EXTI_UART4_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP3, IP3H, 1, __PRIORITY__)
#define EXTI_RTC_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP3, IP3H, 2, __PRIORITY__)
#define EXTI_DMA_M2M_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_M2M_CFG, 2, __PRIORITY__)
#define EXTI_DMA_ADC_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_ADC_CFG, 2, __PRIORITY__)
#define EXTI_DMA_SPI_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_SPI_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART1T_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR1T_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART1R_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR1R_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART2T_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR2T_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART2R_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR2R_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART3T_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR3T_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART3R_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR3R_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART4T_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR4T_CFG, 2, __PRIORITY__)
#define EXTI_DMA_UART4R_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_UR4R_CFG, 2, __PRIORITY__)
#define EXTI_DMA_LCM_SetIntPriority(__PRIORITY__) SFRX_ASSIGN2BIT(DMA_LCM_CFG, 2, __PRIORITY__)
#define EXTI_Port_SetIntPriority(__PORT__, __PRIORITY__) SFRX_DUAL_SET(PIN_IP, PIN_IPH, __PORT__, __PRIORITY__)
#define EXTI_Port_SetIntMode(__PORT__, __PINS__, __PORT_INT_MODE__) do { SFRX_ON(); \

1
include/fw_hal.h
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@ -36,6 +36,7 @@
#if (__CONF_MCU_TYPE == 3 )
#include "fw_pwm.h"
#include "fw_rtc.h"
#include "fw_dma.h"
#endif
#endif

99
include/fw_reg_stc8h.h
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@ -492,6 +492,105 @@ SFR(RSTCFG, 0xFF);
//FA00H-FAFFH
/////////////////////////////////////////////////
#define DMA_M2M_CFG (*(unsigned char volatile __XDATA *)0xfa00)
#define DMA_M2M_CR (*(unsigned char volatile __XDATA *)0xfa01)
#define DMA_M2M_STA (*(unsigned char volatile __XDATA *)0xfa02)
#define DMA_M2M_AMT (*(unsigned char volatile __XDATA *)0xfa03)
#define DMA_M2M_DONE (*(unsigned char volatile __XDATA *)0xfa04)
#define DMA_M2M_TXAH (*(unsigned char volatile __XDATA *)0xfa05)
#define DMA_M2M_TXAL (*(unsigned char volatile __XDATA *)0xfa06)
#define DMA_M2M_RXAH (*(unsigned char volatile __XDATA *)0xfa07)
#define DMA_M2M_RXAL (*(unsigned char volatile __XDATA *)0xfa08)
#define DMA_ADC_CFG (*(unsigned char volatile __XDATA *)0xfa10)
#define DMA_ADC_CR (*(unsigned char volatile __XDATA *)0xfa11)
#define DMA_ADC_STA (*(unsigned char volatile __XDATA *)0xfa12)
#define DMA_ADC_RXAH (*(unsigned char volatile __XDATA *)0xfa17)
#define DMA_ADC_RXAL (*(unsigned char volatile __XDATA *)0xfa18)
#define DMA_ADC_CFG2 (*(unsigned char volatile __XDATA *)0xfa19)
#define DMA_ADC_CHSW0 (*(unsigned char volatile __XDATA *)0xfa1a)
#define DMA_ADC_CHSW1 (*(unsigned char volatile __XDATA *)0xfa1b)
#define DMA_SPI_CFG (*(unsigned char volatile __XDATA *)0xfa20)
#define DMA_SPI_CR (*(unsigned char volatile __XDATA *)0xfa21)
#define DMA_SPI_STA (*(unsigned char volatile __XDATA *)0xfa22)
#define DMA_SPI_AMT (*(unsigned char volatile __XDATA *)0xfa23)
#define DMA_SPI_DONE (*(unsigned char volatile __XDATA *)0xfa24)
#define DMA_SPI_TXAH (*(unsigned char volatile __XDATA *)0xfa25)
#define DMA_SPI_TXAL (*(unsigned char volatile __XDATA *)0xfa26)
#define DMA_SPI_RXAH (*(unsigned char volatile __XDATA *)0xfa27)
#define DMA_SPI_RXAL (*(unsigned char volatile __XDATA *)0xfa28)
#define DMA_SPI_CFG2 (*(unsigned char volatile __XDATA *)0xfa29)
#define DMA_UR1T_CFG (*(unsigned char volatile __XDATA *)0xfa30)
#define DMA_UR1T_CR (*(unsigned char volatile __XDATA *)0xfa31)
#define DMA_UR1T_STA (*(unsigned char volatile __XDATA *)0xfa32)
#define DMA_UR1T_AMT (*(unsigned char volatile __XDATA *)0xfa33)
#define DMA_UR1T_DONE (*(unsigned char volatile __XDATA *)0xfa34)
#define DMA_UR1T_TXAH (*(unsigned char volatile __XDATA *)0xfa35)
#define DMA_UR1T_TXAL (*(unsigned char volatile __XDATA *)0xfa36)
#define DMA_UR1R_CFG (*(unsigned char volatile __XDATA *)0xfa38)
#define DMA_UR1R_CR (*(unsigned char volatile __XDATA *)0xfa39)
#define DMA_UR1R_STA (*(unsigned char volatile __XDATA *)0xfa3a)
#define DMA_UR1R_AMT (*(unsigned char volatile __XDATA *)0xfa3b)
#define DMA_UR1R_DONE (*(unsigned char volatile __XDATA *)0xfa3c)
#define DMA_UR1R_RXAH (*(unsigned char volatile __XDATA *)0xfa3d)
#define DMA_UR1R_RXAL (*(unsigned char volatile __XDATA *)0xfa3e)
#define DMA_UR2T_CFG (*(unsigned char volatile __XDATA *)0xfa40)
#define DMA_UR2T_CR (*(unsigned char volatile __XDATA *)0xfa41)
#define DMA_UR2T_STA (*(unsigned char volatile __XDATA *)0xfa42)
#define DMA_UR2T_AMT (*(unsigned char volatile __XDATA *)0xfa43)
#define DMA_UR2T_DONE (*(unsigned char volatile __XDATA *)0xfa44)
#define DMA_UR2T_TXAH (*(unsigned char volatile __XDATA *)0xfa45)
#define DMA_UR2T_TXAL (*(unsigned char volatile __XDATA *)0xfa46)
#define DMA_UR2R_CFG (*(unsigned char volatile __XDATA *)0xfa48)
#define DMA_UR2R_CR (*(unsigned char volatile __XDATA *)0xfa49)
#define DMA_UR2R_STA (*(unsigned char volatile __XDATA *)0xfa4a)
#define DMA_UR2R_AMT (*(unsigned char volatile __XDATA *)0xfa4b)
#define DMA_UR2R_DONE (*(unsigned char volatile __XDATA *)0xfa4c)
#define DMA_UR2R_RXAH (*(unsigned char volatile __XDATA *)0xfa4d)
#define DMA_UR2R_RXAL (*(unsigned char volatile __XDATA *)0xfa4e)
#define DMA_UR3T_CFG (*(unsigned char volatile __XDATA *)0xfa50)
#define DMA_UR3T_CR (*(unsigned char volatile __XDATA *)0xfa51)
#define DMA_UR3T_STA (*(unsigned char volatile __XDATA *)0xfa52)
#define DMA_UR3T_AMT (*(unsigned char volatile __XDATA *)0xfa53)
#define DMA_UR3T_DONE (*(unsigned char volatile __XDATA *)0xfa54)
#define DMA_UR3T_TXAH (*(unsigned char volatile __XDATA *)0xfa55)
#define DMA_UR3T_TXAL (*(unsigned char volatile __XDATA *)0xfa56)
#define DMA_UR3R_CFG (*(unsigned char volatile __XDATA *)0xfa58)
#define DMA_UR3R_CR (*(unsigned char volatile __XDATA *)0xfa59)
#define DMA_UR3R_STA (*(unsigned char volatile __XDATA *)0xfa5a)
#define DMA_UR3R_AMT (*(unsigned char volatile __XDATA *)0xfa5b)
#define DMA_UR3R_DONE (*(unsigned char volatile __XDATA *)0xfa5c)
#define DMA_UR3R_RXAH (*(unsigned char volatile __XDATA *)0xfa5d)
#define DMA_UR3R_RXAL (*(unsigned char volatile __XDATA *)0xfa5e)
#define DMA_UR4T_CFG (*(unsigned char volatile __XDATA *)0xfa60)
#define DMA_UR4T_CR (*(unsigned char volatile __XDATA *)0xfa61)
#define DMA_UR4T_STA (*(unsigned char volatile __XDATA *)0xfa62)
#define DMA_UR4T_AMT (*(unsigned char volatile __XDATA *)0xfa63)
#define DMA_UR4T_DONE (*(unsigned char volatile __XDATA *)0xfa64)
#define DMA_UR4T_TXAH (*(unsigned char volatile __XDATA *)0xfa65)
#define DMA_UR4T_TXAL (*(unsigned char volatile __XDATA *)0xfa66)
#define DMA_UR4R_CFG (*(unsigned char volatile __XDATA *)0xfa68)
#define DMA_UR4R_CR (*(unsigned char volatile __XDATA *)0xfa69)
#define DMA_UR4R_STA (*(unsigned char volatile __XDATA *)0xfa6a)
#define DMA_UR4R_AMT (*(unsigned char volatile __XDATA *)0xfa6b)
#define DMA_UR4R_DONE (*(unsigned char volatile __XDATA *)0xfa6c)
#define DMA_UR4R_RXAH (*(unsigned char volatile __XDATA *)0xfa6d)
#define DMA_UR4R_RXAL (*(unsigned char volatile __XDATA *)0xfa6e)
#define DMA_LCM_CFG (*(unsigned char volatile __XDATA *)0xfa70)
#define DMA_LCM_CR (*(unsigned char volatile __XDATA *)0xfa71)
#define DMA_LCM_STA (*(unsigned char volatile __XDATA *)0xfa72)
#define DMA_LCM_AMT (*(unsigned char volatile __XDATA *)0xfa73)
#define DMA_LCM_DONE (*(unsigned char volatile __XDATA *)0xfa74)
#define DMA_LCM_TXAH (*(unsigned char volatile __XDATA *)0xfa75)
#define DMA_LCM_TXAL (*(unsigned char volatile __XDATA *)0xfa76)
#define DMA_LCM_RXAH (*(unsigned char volatile __XDATA *)0xfa77)
#define DMA_LCM_RXAL (*(unsigned char volatile __XDATA *)0xfa78)
/////////////////////////////////////////////////

32
include/fw_types.h
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@ -98,6 +98,8 @@ typedef enum
#define SFR_SET(__SFR__, __POS__) ((__SFR__) |= (0x01 << (__POS__)))
#define SFR_RESET(__SFR__, __POS__) ((__SFR__) &= ~(0x01 << (__POS__)))
#define SFR_ASSIGN(__SFR__, __POS__, __VAL__) ((__SFR__) = (__SFR__) & ~(0x01 << (__POS__)) | ((__VAL__) << (__POS__)))
#define SFR_ASSIGN2BIT(__SFR__, __POS__, __VAL__) ((__SFR__) = (__SFR__) & ~(0x03 << (__POS__)) | ((__VAL__ & 0x03) << (__POS__)))
#define SFR_ASSIGN3BIT(__SFR__, __POS__, __VAL__) ((__SFR__) = (__SFR__) & ~(0x07 << (__POS__)) | ((__VAL__ & 0x07) << (__POS__)))
// For dual sfr bit (one for each) operation
#define SFR_DUAL_SET(__SFR0__, __SFR1__, __POS__, __VAL__) do { \
(__SFR0__) = (__SFR0__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x01)? (0x01 << (__POS__)) : 0x00); \
@ -116,16 +118,26 @@ typedef enum
#define SFRX_SET(__SFR__, __POS__) do {SFRX_ON(); (__SFR__) |= (0x01 << (__POS__)); SFRX_OFF();} while(0)
#define SFRX_RESET(__SFR__, __POS__) do {SFRX_ON(); (__SFR__) &= ~(0x01 << (__POS__)); SFRX_OFF();} while(0)
#define SFRX_ASSIGN(__SFR__, __POS__, __VAL__) do { \
SFRX_ON(); \
(__SFR__) = (__SFR__) & ~(0x01 << (__POS__)) | ((__VAL__) << (__POS__)); \
SFRX_OFF(); \
} while(0)
SFRX_ON(); \
(__SFR__) = (__SFR__) & ~(0x01 << (__POS__)) | ((__VAL__) << (__POS__)); \
SFRX_OFF(); \
} while(0)
#define SFRX_ASSIGN2BIT(__SFR__, __POS__, __VAL__) do { \
SFRX_ON(); \
(__SFR__) = (__SFR__) & ~(0x03 << (__POS__)) | ((__VAL__ & 0x03) << (__POS__));\
SFRX_OFF(); \
} while(0)
#define SFRX_ASSIGN3BIT(__SFR__, __POS__, __VAL__) do { \
SFRX_ON(); \
(__SFR__) = (__SFR__) & ~(0x07 << (__POS__)) | ((__VAL__ & 0x07) << (__POS__));\
SFRX_OFF(); \
} while(0)
// For dual xdata sfr bit (one for each) operation
#define SFRX_DUAL_SET(__SFR0__, __SFR1__, __POS__, __VAL__) do { \
SFRX_ON(); \
(__SFR0__) = (__SFR0__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x01)? (0x01 << (__POS__)) : 0x00); \
(__SFR1__) = (__SFR1__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x02)? (0x01 << (__POS__)) : 0x00); \
SFRX_OFF(); \
} while(0)
#define SFRX_DUAL_SET(__SFR0__, __SFR1__, __POS__, __VAL__) do { \
SFRX_ON(); \
(__SFR0__) = (__SFR0__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x01)? (0x01 << (__POS__)) : 0x00); \
(__SFR1__) = (__SFR1__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x02)? (0x01 << (__POS__)) : 0x00); \
SFRX_OFF(); \
} while(0)
#endif

6
src/fw_mem.c
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@ -16,13 +16,13 @@
void MEM_SelectWorkRegGroup(MEM_WorkRegGroup_t WorkRegGroup)
{
RS0 = WorkRegGroup & B00000001;
RS1 = (WorkRegGroup >> 1) & B00000001;
RS0 = WorkRegGroup & 0x01;
RS1 = (WorkRegGroup >> 1) & 0x01;
}
void MEM_SetOnchipExtRAM(HAL_State_t HAL_State)
{
AUXR = AUXR & ~B00000010 | (HAL_State << 1);
AUXR = AUXR & ~(0x01 << 1) | (HAL_State << 1);
}
#if (__CONF_MCU_TYPE == 3 )