feat: demo of spi - nrf24l01 2.4g wireless
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IOsetting
parent
a46612e2c3
commit
e2b29f82b9
204
demo/spi/nrf24l01/nrf24l01.c
Executable file
204
demo/spi/nrf24l01/nrf24l01.c
Executable file
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// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "nrf24l01.h"
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uint8_t __IDATA xbuf[NRF24_PLOAD_WIDTH + 1];
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uint8_t nrf24_state;
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const uint8_t TX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x22};
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const uint8_t RX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x65};
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void NRF24L01_WriteReg(uint8_t reg, uint8_t value)
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{
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NRF_CSN = 0;
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nrf24_state = SPI_TxRx(reg);
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SPI_TxRx(value);
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NRF_CSN = 1;
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}
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uint8_t NRF24L01_ReadReg(uint8_t reg)
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{
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uint8_t value;
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NRF_CSN = 0;
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nrf24_state = SPI_TxRx(reg);
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value = SPI_TxRx(NRF24_CMD_NOP);
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NRF_CSN = 1;
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return value;
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}
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void NRF24L01_ReadToBuf(uint8_t reg, uint8_t *pBuf, uint8_t len)
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{
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uint8_t u8_ctr;
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NRF_CSN = 0;
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nrf24_state = SPI_TxRx(reg);
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for (u8_ctr = 0; u8_ctr < len; u8_ctr++)
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pBuf[u8_ctr] = SPI_TxRx(NRF24_CMD_NOP);
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NRF_CSN = 1;
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}
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void NRF24L01_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len)
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{
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uint8_t u8_ctr;
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NRF_CSN = 0;
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nrf24_state = SPI_TxRx(reg);
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for (u8_ctr = 0; u8_ctr < len; u8_ctr++)
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SPI_TxRx(*pBuf++);
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NRF_CSN = 1;
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}
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void NRF24L01_PrintBuf(uint8_t *buf)
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{
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uint8_t i;
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for (i = 0; i < NRF24_PLOAD_WIDTH; i++)
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{
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UART1_TxHex(buf[i]);
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}
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UART1_TxString("\r\n");
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}
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/**
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* Flush the RX FIFO
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*/
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void NRF24L01_FlushRX(void)
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{
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NRF24L01_WriteReg(NRF24_CMD_FLUSH_RX, NRF24_CMD_NOP);
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}
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/**
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* Flush the TX FIFO
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*/
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void NRF24L01_FlushTX(void)
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{
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NRF24L01_WriteReg(NRF24_CMD_FLUSH_TX, NRF24_CMD_NOP);
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}
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void NRF24L01_CheckFlag(uint8_t *tx_ds, uint8_t *max_rt, uint8_t *rx_dr)
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{
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// Read the status & reset the status in one easy call
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_STATUS, NRF24_FLAG_RX_DREADY|NRF24_FLAG_TX_DSENT|NRF24_FLAG_MAX_RT);
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// Report to the user what happened
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*tx_ds = nrf24_state & NRF24_FLAG_TX_DSENT;
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*max_rt = nrf24_state & NRF24_FLAG_MAX_RT;
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*rx_dr = nrf24_state & NRF24_FLAG_RX_DREADY;
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}
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uint8_t NRF24L01_RxAvailable(uint8_t* pipe_num)
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{
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uint8_t pipe;
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nrf24_state = NRF24L01_ReadReg(NRF24_REG_STATUS);
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pipe = (nrf24_state >> 1) & 0x07;
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if (pipe > 5)
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return 0;
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// If the caller wants the pipe number, include that
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if (pipe_num)
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*pipe_num = pipe;
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return 1;
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}
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void NRF24L01_HandelIrqFlag(uint8_t *buf)
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{
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uint8_t tx_ds, max_rt, rx_dr, pipe_num;
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NRF24L01_CheckFlag(&tx_ds, &max_rt, &rx_dr);
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if (NRF24L01_RxAvailable(&pipe_num) == 1)
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{
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NRF24L01_ReadToBuf(NRF24_CMD_R_RX_PAYLOAD, buf, NRF24_PLOAD_WIDTH);
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}
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UART1_TxHex(tx_ds);
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UART1_TxChar(' ');
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UART1_TxHex(max_rt);
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UART1_TxChar(' ');
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UART1_TxHex(rx_dr);
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UART1_TxChar(' ');
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UART1_TxHex(pipe_num);
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UART1_TxString("\r\n");
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NRF24L01_PrintBuf(xbuf);
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}
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void NRF24L01_Tx(uint8_t *txbuf)
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{
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NRF_CE = 0;
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0E);
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NRF24L01_WriteFromBuf(NRF24_CMD_W_TX_PAYLOAD, txbuf, NRF24_PLOAD_WIDTH);
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NRF_CE = 1;
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SYS_Delay(10); // for reliable DS state when SETUP_RETR is 0x13
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NRF_CE = 0;
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0F);
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NRF_CE = 1;
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}
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void NRF24L01_StartFastWrite(const void* txbuf)
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{
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NRF24L01_WriteFromBuf(NRF24_CMD_W_TX_PAYLOAD, txbuf, NRF24_PLOAD_WIDTH);
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NRF_CE = 1;
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}
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uint8_t NRF24L01_WriteFast(const void* txbuf)
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{
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//Blocking only if FIFO is full. This will loop and block until TX is successful or fail
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while ((NRF24L01_ReadReg(NRF24_REG_STATUS) & NRF24_FLAG_TX_FULL)) {
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if (nrf24_state & NRF24_FLAG_MAX_RT) {
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return 0;
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}
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}
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NRF24L01_StartFastWrite(txbuf);
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return 1;
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}
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void NRF24L01_ResetTX(void)
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{
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_STATUS, NRF24_FLAG_MAX_RT);//Clear max retry flag
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NRF_CE = 0;
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NRF_CE = 1;
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}
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uint8_t NRF24L01_Check(void)
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{
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uint8_t i;
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const uint8_t *ptr = (const uint8_t *)NRF24_TEST_ADDR;
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NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER | NRF24_REG_TX_ADDR, ptr, NRF24_ADDR_WIDTH);
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NRF24L01_ReadToBuf(NRF24_CMD_R_REGISTER | NRF24_REG_TX_ADDR, xbuf, NRF24_ADDR_WIDTH);
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for (i = 0; i < NRF24_ADDR_WIDTH; i++) {
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UART1_TxHex(xbuf[i]);
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if (xbuf[i] != *ptr++) return 1;
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}
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return 0;
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}
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void NRF24L01_Init(NRF24_MODE mode)
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{
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NRF_CE = 0;
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NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_TX_ADDR, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH);
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RX_PW_P0, NRF24_PLOAD_WIDTH);
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NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_RX_ADDR_P0, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH);
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RX_PW_P1, NRF24_PLOAD_WIDTH);
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NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_RX_ADDR_P1, (uint8_t *)RX_ADDRESS, NRF24_ADDR_WIDTH);
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_EN_AA, 0x3f);
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_EN_RXADDR, 0x3f);
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_SETUP_RETR, 0x13);
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RF_CH, 40);
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RF_SETUP, 0x07);
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switch (mode)
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{
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case NRF24_MODE_TX:
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0E);
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break;
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case NRF24_MODE_RX:
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default:
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NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0F);
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break;
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}
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NRF_CE = 1;
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}
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149
demo/spi/nrf24l01/nrf24l01.h
Executable file
149
demo/spi/nrf24l01/nrf24l01.h
Executable file
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// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __FW_RNF24L01_H__
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#define __FW_RNF24L01_H__
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#include "fw_hal.h"
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#define NRF_CSN P35
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#define NRF_MOSI P34
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#define NRF_MISO P33
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#define NRF_SCK P32
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#define NRF_IRQ P36
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#define NRF_CE P37
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/********** SPI(nRF24L01) commands ***********/
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//
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#define NRF24_CMD_R_REGISTER 0x00 // [000A AAAA] Register read
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#define NRF24_CMD_W_REGISTER 0x20 // [001A AAAA] Register write
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#define NRF24_CMD_R_RX_PAYLOAD 0x61 // Read RX payload
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#define NRF24_CMD_W_TX_PAYLOAD 0xA0 // Write TX payload
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#define NRF24_CMD_FLUSH_TX 0xE1 // Flush TX FIFO
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#define NRF24_CMD_FLUSH_RX 0xE2 // Flush RX FIFO
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#define NRF24_CMD_REUSE_TX_PL 0xE3 // Reuse TX payload
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#define NRF24_CMD_R_RX_PL_WID 0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO.
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#define NRF24_CMD_W_ACK_PAYLOAD 0xA8 // [1010 1PPP] Write ACK Payload to be with ACK packet on PIPE PPP
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#define NRF24_CMD_W_TX_PAYLOAD_NOACK 0xB0 //Write TX payload and disable AUTOACK
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#define NRF24_CMD_NOP 0xFF // No operation (used for reading status register)
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#define NRF24_CMD_ACTIVATE 0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features
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#define NRF24_CMD_LOCK_UNLOCK 0x50 // Lock/unlock exclusive features
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// SPI(nRF24L01) register address definitions
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#define NRF24_REG_CONFIG 0x00 // Configuration register
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#define NRF24_REG_EN_AA 0x01 // Enable "Auto acknowledgment"
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#define NRF24_REG_EN_RXADDR 0x02 // Enable RX addresses
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#define NRF24_REG_SETUP_AW 0x03 // Setup of address widths
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#define NRF24_REG_SETUP_RETR 0x04 // Setup of automatic re-transmit
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#define NRF24_REG_RF_CH 0x05 // RF channel
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#define NRF24_REG_RF_SETUP 0x06 // RF setup
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#define NRF24_REG_STATUS 0x07 // Status register
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#define NRF24_REG_OBSERVE_TX 0x08 // Transmit observe register
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#define NRF24_REG_RPD 0x09 // Received power detector
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#define NRF24_REG_RX_ADDR_P0 0x0A // Receive address data pipe 0
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#define NRF24_REG_RX_ADDR_P1 0x0B // Receive address data pipe 1
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#define NRF24_REG_RX_ADDR_P2 0x0C // Receive address data pipe 2
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#define NRF24_REG_RX_ADDR_P3 0x0D // Receive address data pipe 3
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#define NRF24_REG_RX_ADDR_P4 0x0E // Receive address data pipe 4
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#define NRF24_REG_RX_ADDR_P5 0x0F // Receive address data pipe 5
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#define NRF24_REG_TX_ADDR 0x10 // Transmit address
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#define NRF24_REG_RX_PW_P0 0x11 // Number of bytes in RX payload in data pipe 0
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#define NRF24_REG_RX_PW_P1 0x12 // Number of bytes in RX payload in data pipe 1
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#define NRF24_REG_RX_PW_P2 0x13 // Number of bytes in RX payload in data pipe 2
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#define NRF24_REG_RX_PW_P3 0x14 // Number of bytes in RX payload in data pipe 3
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#define NRF24_REG_RX_PW_P4 0x15 // Number of bytes in RX payload in data pipe 4
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#define NRF24_REG_RX_PW_P5 0x16 // Number of bytes in RX payload in data pipe 5
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#define NRF24_REG_FIFO_STATUS 0x17 // FIFO status register
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#define NRF24_REG_DYNPD 0x1C // Enable dynamic payload length
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#define NRF24_REG_FEATURE 0x1D // Feature register
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// Register bits definitions
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#define NRF24_CONFIG_PRIM_RX 0x01 // PRIM_RX bit in CONFIG register
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#define NRF24_CONFIG_PWR_UP 0x02 // PWR_UP bit in CONFIG register
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#define NRF24_FEATURE_EN_DYN_ACK 0x01 // EN_DYN_ACK bit in FEATURE register
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#define NRF24_FEATURE_EN_ACK_PAY 0x02 // EN_ACK_PAY bit in FEATURE register
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#define NRF24_FEATURE_EN_DPL 0x04 // EN_DPL bit in FEATURE register
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#define NRF24_FLAG_RX_DREADY 0x40 // RX_DR bit (data ready RX FIFO interrupt)
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#define NRF24_FLAG_TX_DSENT 0x20 // TX_DS bit (data sent TX FIFO interrupt)
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#define NRF24_FLAG_MAX_RT 0x10 // MAX_RT bit (maximum number of TX re-transmits interrupt)
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#define NRF24_FLAG_TX_FULL 0x01 // 1:TX FIFO full
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// Register masks definitions
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#define NRF24_MASK_REG_MAP 0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands
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#define NRF24_MASK_CRC 0x0C // Mask for CRC bits [3:2] in CONFIG register
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#define NRF24_MASK_STATUS_IRQ 0x70 // Mask for all IRQ bits in STATUS register
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#define NRF24_MASK_RF_PWR 0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register
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#define NRF24_MASK_RX_P_NO 0x0E // Mask RX_P_NO[3:1] bits in STATUS register
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#define NRF24_MASK_DATARATE 0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register
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#define NRF24_MASK_EN_RX 0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register
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#define NRF24_MASK_RX_PW 0x3F // Mask [5:0] bits in RX_PW_Px register
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#define NRF24_MASK_RETR_ARD 0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register
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#define NRF24_MASK_RETR_ARC 0x0F // Mask for ARC[3:0] bits in SETUP_RETR register
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#define NRF24_MASK_RXFIFO 0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register
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#define NRF24_MASK_TXFIFO 0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register
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#define NRF24_MASK_PLOS_CNT 0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register
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#define NRF24_MASK_ARC_CNT 0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register
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#define NRF24_ADDR_WIDTH 5 // RX/TX address width
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#define NRF24_PLOAD_WIDTH 32 // Payload width
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#define NRF24_TEST_ADDR "nRF24"
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typedef enum
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{
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NRF24_MODE_RX = 0x00,
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NRF24_MODE_TX = 0x01
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} NRF24_MODE;
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typedef enum
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{
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NRF24_SCEN_RX = 0x00,
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NRF24_SCEN_TX = 0x01,
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NRF24_SCEN_HALF_DUPLEX = 0x02
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} NRF24_SCEN;
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void NRF24L01_WriteReg(uint8_t reg, uint8_t value);
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uint8_t NRF24L01_ReadReg(uint8_t reg);
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void NRF24L01_ReadToBuf(uint8_t reg, uint8_t *pBuf, uint8_t len);
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void NRF24L01_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len);
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void NRF24L01_PrintBuf(uint8_t *buf);
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/**
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* Flush the RX FIFO
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*/
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void NRF24L01_FlushRX(void);
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/**
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* Flush the TX FIFO
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*/
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void NRF24L01_FlushTX(void);
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void NRF24L01_CheckFlag(uint8_t *tx_ds, uint8_t *max_rt, uint8_t *rx_dr);
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uint8_t NRF24L01_RxAvailable(uint8_t* pipe_num);
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void NRF24L01_HandelIrqFlag(uint8_t *buf);
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void NRF24L01_Tx(uint8_t *txbuf);
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void NRF24L01_StartFastWrite(const void* txbuf);
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uint8_t NRF24L01_WriteFast(const void* txbuf);
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void NRF24L01_ResetTX(void);
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uint8_t NRF24L01_Check(void);
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void NRF24L01_Init(NRF24_MODE mode);
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#endif
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151
demo/spi/nrf24l01/nrf24l01_stc8h3k.c
Normal file
151
demo/spi/nrf24l01/nrf24l01_stc8h3k.c
Normal file
@ -0,0 +1,151 @@
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||||
// Copyright 2021 IOsetting <iosetting(at)outlook.com>
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/**
|
||||
* Example code of SPI driving NRF24L01 module
|
||||
*
|
||||
* Pin connection:
|
||||
* P35(SS, Ignored) => CSN
|
||||
* P34(MOSI) => MOSI
|
||||
* P33(MISO) => MISO
|
||||
* P32(SPCLK) => CLK
|
||||
* P36(INT2) => IRQ
|
||||
* P37(IO) => CE
|
||||
*
|
||||
* test-board: Minimum System; test-MCU: STC8H3K32S2
|
||||
*/
|
||||
|
||||
#include "nrf24l01.h"
|
||||
#include <stdio.h>
|
||||
|
||||
const NRF24_SCEN CURRENT_SCEN = NRF24_SCEN_HALF_DUPLEX;
|
||||
extern uint8_t __IDATA xbuf[NRF24_PLOAD_WIDTH + 1];
|
||||
|
||||
void SPI_Init(void)
|
||||
{
|
||||
// ST7567 doesn't work if SPI frequency is too high
|
||||
SPI_SetClockPrescaler(SPI_ClockPreScaler_16);
|
||||
// Clock idles low
|
||||
SPI_SetClockPolarity(HAL_State_OFF);
|
||||
// Data transfer is driven by lower SS pin
|
||||
SPI_SetClockPhase(SPI_ClockPhase_LeadingEdge);
|
||||
// MSB first
|
||||
SPI_SetDataOrder(SPI_DataOrder_MSB);
|
||||
// Define the output pins
|
||||
SPI_SetPort(SPI_AlterPort_P35_P34_P33_P32);
|
||||
// Ignore SS pin, use MSTR to swith between master/slave mode
|
||||
SPI_IgnoreSlaveSelect(HAL_State_ON);
|
||||
// Master mode
|
||||
SPI_SetMasterMode(HAL_State_ON);
|
||||
// Start SPI
|
||||
SPI_SetEnableState(HAL_State_ON);
|
||||
}
|
||||
|
||||
void GPIO_Init(void)
|
||||
{
|
||||
// Configure GPIO pins before SPI and device
|
||||
// MISO(P33) MOSI(P34)
|
||||
GPIO_P3_SetMode(GPIO_Pin_4, GPIO_Mode_InOut_QBD);
|
||||
// SCLK(P32) CSN(P35) CE(P37)
|
||||
GPIO_P3_SetMode(GPIO_Pin_2|GPIO_Pin_5|GPIO_Pin_7, GPIO_Mode_Output_PP);
|
||||
// IRQ(P36)
|
||||
GPIO_P3_SetMode(GPIO_Pin_6, GPIO_Mode_Input_HIP);
|
||||
}
|
||||
|
||||
void INT_Init()
|
||||
{
|
||||
EXTI_Int2_SetIntState(HAL_State_ON);
|
||||
EXTI_Global_SetIntState(HAL_State_ON);
|
||||
}
|
||||
|
||||
INTERRUPT(Int2_Routine, EXTI_VectInt2)
|
||||
{
|
||||
NRF24L01_HandelIrqFlag(xbuf);
|
||||
}
|
||||
|
||||
void main(void)
|
||||
{
|
||||
uint8_t __CODE tmp[] = {
|
||||
0x1F, 0x80, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
|
||||
0x21, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x28,
|
||||
0x31, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x38,
|
||||
0x41, 0x12, 0x13, 0x14, 0x15, 0x16, 0x37, 0x48};
|
||||
uint8_t succ = 0, err = 0;
|
||||
|
||||
SYS_SetClock();
|
||||
|
||||
GPIO_Init();
|
||||
// UART1, baud 115200, baud source Timer1, 1T mode, no interrupt
|
||||
UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer1, HAL_State_ON, 115200);
|
||||
UART1_TxString("UART Initialized\r\n");
|
||||
|
||||
SPI_Init();
|
||||
UART1_TxString("SPI Initialized\r\n");
|
||||
|
||||
while (NRF24L01_Check() == 1)
|
||||
{
|
||||
UART1_TxString("Check failed\r\n");
|
||||
SYS_Delay(1000);
|
||||
}
|
||||
UART1_TxString("NRF24L01 Checked\r\n");
|
||||
|
||||
switch (CURRENT_SCEN)
|
||||
{
|
||||
case NRF24_SCEN_TX:
|
||||
NRF24L01_Init(NRF24_MODE_TX);
|
||||
UART1_TxString("NRF24L01 Initialized\r\n");
|
||||
while (1)
|
||||
{
|
||||
if (NRF24L01_WriteFast(tmp) == 0)
|
||||
{
|
||||
NRF24L01_ResetTX();
|
||||
err++;
|
||||
}
|
||||
else
|
||||
{
|
||||
succ++;
|
||||
}
|
||||
if (err >= 255 || succ >= 255)
|
||||
{
|
||||
UART1_TxHex(err);
|
||||
UART1_TxHex(succ);
|
||||
UART1_TxChar('.');
|
||||
err = 0;
|
||||
succ = 0;
|
||||
}
|
||||
SYS_Delay(50);
|
||||
}
|
||||
break;
|
||||
|
||||
case NRF24_SCEN_RX:
|
||||
NRF24L01_Init(NRF24_MODE_RX);
|
||||
INT_Init();
|
||||
while (1);
|
||||
break;
|
||||
|
||||
case NRF24_SCEN_HALF_DUPLEX:
|
||||
NRF24L01_Init(NRF24_MODE_RX);
|
||||
INT_Init();
|
||||
while (1)
|
||||
{
|
||||
NRF24L01_Tx(tmp);
|
||||
SYS_Delay(1000);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
UART1_TxString("Unknown scen\r\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -12,8 +12,8 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef __ST7567_H_
|
||||
#define __ST7567_H_
|
||||
#ifndef __FW_ST7567__
|
||||
#define __FW_ST7567__
|
||||
|
||||
#include "fw_hal.h"
|
||||
|
||||
|
||||
@ -122,12 +122,9 @@ typedef enum
|
||||
#define EXTI_SPI_SetIntState(__STATE__) SFR_ASSIGN(IE2, 1, __STATE__)
|
||||
#define EXTI_UART2_SetIntState(__STATE__) SFR_ASSIGN(IE2, 0, __STATE__)
|
||||
|
||||
#define EXTI_INT_Int4_ON SFR_SET(INTCLKO, 6)
|
||||
#define EXTI_INT_Int4_OFF SFR_RESET(INTCLKO, 6)
|
||||
#define EXTI_INT_Int3_ON SFR_SET(INTCLKO, 5)
|
||||
#define EXTI_INT_Int3_OFF SFR_RESET(INTCLKO, 5)
|
||||
#define EXTI_INT_Int2_ON SFR_SET(INTCLKO, 4)
|
||||
#define EXTI_INT_Int2_OFF SFR_RESET(INTCLKO, 4)
|
||||
#define EXTI_Int4_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 6, __STATE__)
|
||||
#define EXTI_Int3_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 5, __STATE__)
|
||||
#define EXTI_Int2_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 4, __STATE__)
|
||||
|
||||
#define EXTI_INT_CompRise_ON SFR_SET(CMPCR1, 5)
|
||||
#define EXTI_INT_CompRise_OFF SFR_RESET(CMPCR1, 5)
|
||||
|
||||
@ -12,8 +12,8 @@
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef __IO_REG_BASE_H__
|
||||
#define __IO_REG_BASE_H__
|
||||
#ifndef __FW_REG_BASE_H__
|
||||
#define __FW_REG_BASE_H__
|
||||
|
||||
#if defined (SDCC) || defined (__SDCC)
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#ifndef __IO_REG_STC8G_H__
|
||||
#define __IO_REG_STC8G_H__
|
||||
#ifndef __FW_REG_STC8G_H__
|
||||
#define __FW_REG_STC8G_H__
|
||||
|
||||
#include "fw_reg_base.h"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#ifndef __IO_REG_STC8H_H__
|
||||
#define __IO_REG_STC8H_H__
|
||||
#ifndef __FW_REG_STC8H_H__
|
||||
#define __FW_REG_STC8H_H__
|
||||
|
||||
#include "fw_reg_base.h"
|
||||
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
|
||||
#define UART_RX_BUFF_SIZE 0x20
|
||||
|
||||
int16_t UART_Timer_InitValueCalculate(uint32_t sysclk, HAL_State_t _1TMode, uint32_t baudrate);
|
||||
|
||||
|
||||
/**************************************************************************** /
|
||||
* UART1
|
||||
|
||||
@ -16,18 +16,13 @@
|
||||
#include "fw_tim.h"
|
||||
#include "fw_sys.h"
|
||||
|
||||
static const char hexTable[16] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'};
|
||||
char wptr, rptr, UART1_RxBuffer[UART_RX_BUFF_SIZE];
|
||||
__CODE static char hexTable[16] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'};
|
||||
__IDATA char wptr, rptr, UART1_RxBuffer[UART_RX_BUFF_SIZE];
|
||||
__BIT busy;
|
||||
|
||||
|
||||
/**************************************************************************** /
|
||||
* UART1
|
||||
*/
|
||||
|
||||
int16_t _UART1_Timer_InitValueCalculate(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
int16_t UART_Timer_InitValueCalculate(uint32_t sysclk, HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint32_t value, sysclk = SYS_GetSysClock();
|
||||
uint32_t value;
|
||||
value = sysclk / (4 * baudrate);
|
||||
if (!_1TMode)
|
||||
value = value / 12;
|
||||
@ -37,9 +32,12 @@ int16_t _UART1_Timer_InitValueCalculate(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
return 0xFFFF - value + 1;
|
||||
}
|
||||
|
||||
void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate)
|
||||
/**************************************************************************** /
|
||||
* UART1
|
||||
*/
|
||||
|
||||
void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, int16_t init)
|
||||
{
|
||||
uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate);
|
||||
UART1_SetBaudSource(baudSource);
|
||||
// Timer1 configuration. Mode0 only, mode2 is covered by mode0 so it is unnecessary.
|
||||
if (baudSource == UART1_BaudSource_Timer1)
|
||||
@ -60,14 +58,22 @@ void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, ui
|
||||
}
|
||||
void UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint16_t init;
|
||||
uint32_t sysclk;
|
||||
SM0=0; SM1=1;
|
||||
_UART1_ConfigDynUart(baudSource, _1TMode, baudrate);
|
||||
sysclk = SYS_GetSysClock();
|
||||
init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate);
|
||||
_UART1_ConfigDynUart(baudSource, _1TMode, init);
|
||||
}
|
||||
|
||||
void UART1_ConfigMode3Dyn9bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint16_t init;
|
||||
uint32_t sysclk;
|
||||
SM0=1; SM1=1;
|
||||
_UART1_ConfigDynUart(baudSource, _1TMode, baudrate);
|
||||
sysclk = SYS_GetSysClock();
|
||||
init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate);
|
||||
_UART1_ConfigDynUart(baudSource, _1TMode, init);
|
||||
}
|
||||
|
||||
void UART1_InterruptHandler(void)
|
||||
@ -128,7 +134,10 @@ void UART1_TxString(uint8_t *str)
|
||||
|
||||
void UART2_Config(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate);
|
||||
uint16_t init;
|
||||
uint32_t sysclk;
|
||||
sysclk = SYS_GetSysClock();
|
||||
init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate);
|
||||
// Timer2: 1T mode and initial value. prescaler is ignored, no interrupt.
|
||||
TIM_Timer2_Set1TMode(_1TMode);
|
||||
TIM_Timer2_SetInitValue(init >> 8, init & 0xFF);
|
||||
@ -161,8 +170,10 @@ void UART2_TxString(uint8_t *str)
|
||||
void UART3_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint16_t init;
|
||||
uint32_t sysclk;
|
||||
UART3_SetBaudSource(0x00);
|
||||
init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate);
|
||||
sysclk = SYS_GetSysClock();
|
||||
init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate);
|
||||
// Timer2: 1T mode and initial value. prescaler is ignored, no interrupt.
|
||||
TIM_Timer2_Set1TMode(_1TMode);
|
||||
TIM_Timer2_SetInitValue(init >> 8, init & 0xFF);
|
||||
@ -172,8 +183,10 @@ void UART3_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
void UART3_ConfigOnTimer3(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint16_t init;
|
||||
uint32_t sysclk;
|
||||
UART3_SetBaudSource(0x01);
|
||||
init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate);
|
||||
sysclk = SYS_GetSysClock();
|
||||
init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate);
|
||||
// Timer3: 1T mode and initial value. prescaler is ignored, no interrupt.
|
||||
TIM_Timer3_Set1TMode(_1TMode);
|
||||
TIM_Timer3_SetInitValue(init >> 8, init & 0xFF);
|
||||
@ -188,8 +201,10 @@ void UART3_ConfigOnTimer3(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
void UART4_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint16_t init;
|
||||
uint32_t sysclk;
|
||||
UART4_SetBaudSource(0x00);
|
||||
init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate);
|
||||
sysclk = SYS_GetSysClock();
|
||||
init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate);
|
||||
TIM_Timer2_Set1TMode(_1TMode);
|
||||
TIM_Timer2_SetInitValue(init >> 8, init & 0xFF);
|
||||
TIM_Timer2_SetRunState(HAL_State_ON);
|
||||
@ -198,8 +213,10 @@ void UART4_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
void UART4_ConfigOnTimer4(HAL_State_t _1TMode, uint32_t baudrate)
|
||||
{
|
||||
uint16_t init;
|
||||
uint32_t sysclk;
|
||||
UART4_SetBaudSource(0x01);
|
||||
init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate);
|
||||
sysclk = SYS_GetSysClock();
|
||||
init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate);
|
||||
TIM_Timer4_Set1TMode(_1TMode);
|
||||
TIM_Timer4_SetInitValue(init >> 8, init & 0xFF);
|
||||
TIM_Timer4_SetRunState(HAL_State_ON);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user