From e2b29f82b9c0a40665aea26e6e465c874e16e76a Mon Sep 17 00:00:00 2001 From: IOsetting Date: Mon, 3 Jan 2022 14:13:59 +0800 Subject: [PATCH] feat: demo of spi - nrf24l01 2.4g wireless --- demo/spi/nrf24l01/nrf24l01.c | 204 +++++++++++++++++++++++++++ demo/spi/nrf24l01/nrf24l01.h | 149 +++++++++++++++++++ demo/spi/nrf24l01/nrf24l01_stc8h3k.c | 151 ++++++++++++++++++++ demo/spi/st7567/st7567.h | 4 +- include/fw_exti.h | 9 +- include/fw_reg_base.h | 4 +- include/fw_reg_stc8g.h | 4 +- include/fw_reg_stc8h.h | 4 +- include/fw_uart.h | 2 + src/fw_uart.c | 53 ++++--- 10 files changed, 552 insertions(+), 32 deletions(-) create mode 100755 demo/spi/nrf24l01/nrf24l01.c create mode 100755 demo/spi/nrf24l01/nrf24l01.h create mode 100644 demo/spi/nrf24l01/nrf24l01_stc8h3k.c diff --git a/demo/spi/nrf24l01/nrf24l01.c b/demo/spi/nrf24l01/nrf24l01.c new file mode 100755 index 0000000..b1aea84 --- /dev/null +++ b/demo/spi/nrf24l01/nrf24l01.c @@ -0,0 +1,204 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "nrf24l01.h" + +uint8_t __IDATA xbuf[NRF24_PLOAD_WIDTH + 1]; +uint8_t nrf24_state; + +const uint8_t TX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x22}; +const uint8_t RX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x65}; + +void NRF24L01_WriteReg(uint8_t reg, uint8_t value) +{ + NRF_CSN = 0; + nrf24_state = SPI_TxRx(reg); + SPI_TxRx(value); + NRF_CSN = 1; +} + +uint8_t NRF24L01_ReadReg(uint8_t reg) +{ + uint8_t value; + NRF_CSN = 0; + nrf24_state = SPI_TxRx(reg); + value = SPI_TxRx(NRF24_CMD_NOP); + NRF_CSN = 1; + return value; +} + +void NRF24L01_ReadToBuf(uint8_t reg, uint8_t *pBuf, uint8_t len) +{ + uint8_t u8_ctr; + NRF_CSN = 0; + nrf24_state = SPI_TxRx(reg); + for (u8_ctr = 0; u8_ctr < len; u8_ctr++) + pBuf[u8_ctr] = SPI_TxRx(NRF24_CMD_NOP); + NRF_CSN = 1; +} + +void NRF24L01_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len) +{ + uint8_t u8_ctr; + NRF_CSN = 0; + nrf24_state = SPI_TxRx(reg); + for (u8_ctr = 0; u8_ctr < len; u8_ctr++) + SPI_TxRx(*pBuf++); + NRF_CSN = 1; +} + +void NRF24L01_PrintBuf(uint8_t *buf) +{ + uint8_t i; + for (i = 0; i < NRF24_PLOAD_WIDTH; i++) + { + UART1_TxHex(buf[i]); + } + UART1_TxString("\r\n"); +} + +/** +* Flush the RX FIFO +*/ +void NRF24L01_FlushRX(void) +{ + NRF24L01_WriteReg(NRF24_CMD_FLUSH_RX, NRF24_CMD_NOP); +} + +/** +* Flush the TX FIFO +*/ +void NRF24L01_FlushTX(void) +{ + NRF24L01_WriteReg(NRF24_CMD_FLUSH_TX, NRF24_CMD_NOP); +} + +void NRF24L01_CheckFlag(uint8_t *tx_ds, uint8_t *max_rt, uint8_t *rx_dr) +{ + // Read the status & reset the status in one easy call + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_STATUS, NRF24_FLAG_RX_DREADY|NRF24_FLAG_TX_DSENT|NRF24_FLAG_MAX_RT); + // Report to the user what happened + *tx_ds = nrf24_state & NRF24_FLAG_TX_DSENT; + *max_rt = nrf24_state & NRF24_FLAG_MAX_RT; + *rx_dr = nrf24_state & NRF24_FLAG_RX_DREADY; +} + +uint8_t NRF24L01_RxAvailable(uint8_t* pipe_num) +{ + uint8_t pipe; + nrf24_state = NRF24L01_ReadReg(NRF24_REG_STATUS); + pipe = (nrf24_state >> 1) & 0x07; + if (pipe > 5) + return 0; + // If the caller wants the pipe number, include that + if (pipe_num) + *pipe_num = pipe; + + return 1; +} + +void NRF24L01_HandelIrqFlag(uint8_t *buf) +{ + uint8_t tx_ds, max_rt, rx_dr, pipe_num; + NRF24L01_CheckFlag(&tx_ds, &max_rt, &rx_dr); + if (NRF24L01_RxAvailable(&pipe_num) == 1) + { + NRF24L01_ReadToBuf(NRF24_CMD_R_RX_PAYLOAD, buf, NRF24_PLOAD_WIDTH); + } + UART1_TxHex(tx_ds); + UART1_TxChar(' '); + UART1_TxHex(max_rt); + UART1_TxChar(' '); + UART1_TxHex(rx_dr); + UART1_TxChar(' '); + UART1_TxHex(pipe_num); + UART1_TxString("\r\n"); + NRF24L01_PrintBuf(xbuf); +} + +void NRF24L01_Tx(uint8_t *txbuf) +{ + NRF_CE = 0; + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0E); + NRF24L01_WriteFromBuf(NRF24_CMD_W_TX_PAYLOAD, txbuf, NRF24_PLOAD_WIDTH); + NRF_CE = 1; + SYS_Delay(10); // for reliable DS state when SETUP_RETR is 0x13 + NRF_CE = 0; + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0F); + NRF_CE = 1; +} + +void NRF24L01_StartFastWrite(const void* txbuf) +{ + NRF24L01_WriteFromBuf(NRF24_CMD_W_TX_PAYLOAD, txbuf, NRF24_PLOAD_WIDTH); + NRF_CE = 1; +} + +uint8_t NRF24L01_WriteFast(const void* txbuf) +{ + //Blocking only if FIFO is full. This will loop and block until TX is successful or fail + while ((NRF24L01_ReadReg(NRF24_REG_STATUS) & NRF24_FLAG_TX_FULL)) { + if (nrf24_state & NRF24_FLAG_MAX_RT) { + return 0; + } + } + NRF24L01_StartFastWrite(txbuf); + return 1; +} + +void NRF24L01_ResetTX(void) +{ + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_STATUS, NRF24_FLAG_MAX_RT);//Clear max retry flag + NRF_CE = 0; + NRF_CE = 1; +} + +uint8_t NRF24L01_Check(void) +{ + uint8_t i; + const uint8_t *ptr = (const uint8_t *)NRF24_TEST_ADDR; + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER | NRF24_REG_TX_ADDR, ptr, NRF24_ADDR_WIDTH); + NRF24L01_ReadToBuf(NRF24_CMD_R_REGISTER | NRF24_REG_TX_ADDR, xbuf, NRF24_ADDR_WIDTH); + for (i = 0; i < NRF24_ADDR_WIDTH; i++) { + UART1_TxHex(xbuf[i]); + if (xbuf[i] != *ptr++) return 1; + } + return 0; +} + +void NRF24L01_Init(NRF24_MODE mode) +{ + NRF_CE = 0; + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_TX_ADDR, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RX_PW_P0, NRF24_PLOAD_WIDTH); + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_RX_ADDR_P0, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RX_PW_P1, NRF24_PLOAD_WIDTH); + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_RX_ADDR_P1, (uint8_t *)RX_ADDRESS, NRF24_ADDR_WIDTH); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_EN_AA, 0x3f); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_EN_RXADDR, 0x3f); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_SETUP_RETR, 0x13); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RF_CH, 40); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RF_SETUP, 0x07); + switch (mode) + { + case NRF24_MODE_TX: + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0E); + break; + case NRF24_MODE_RX: + default: + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0F); + break; + } + NRF_CE = 1; +} \ No newline at end of file diff --git a/demo/spi/nrf24l01/nrf24l01.h b/demo/spi/nrf24l01/nrf24l01.h new file mode 100755 index 0000000..6b7289b --- /dev/null +++ b/demo/spi/nrf24l01/nrf24l01.h @@ -0,0 +1,149 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __FW_RNF24L01_H__ +#define __FW_RNF24L01_H__ + +#include "fw_hal.h" + +#define NRF_CSN P35 +#define NRF_MOSI P34 +#define NRF_MISO P33 +#define NRF_SCK P32 +#define NRF_IRQ P36 +#define NRF_CE P37 + +/********** SPI(nRF24L01) commands ***********/ +// +#define NRF24_CMD_R_REGISTER 0x00 // [000A AAAA] Register read +#define NRF24_CMD_W_REGISTER 0x20 // [001A AAAA] Register write +#define NRF24_CMD_R_RX_PAYLOAD 0x61 // Read RX payload +#define NRF24_CMD_W_TX_PAYLOAD 0xA0 // Write TX payload +#define NRF24_CMD_FLUSH_TX 0xE1 // Flush TX FIFO +#define NRF24_CMD_FLUSH_RX 0xE2 // Flush RX FIFO +#define NRF24_CMD_REUSE_TX_PL 0xE3 // Reuse TX payload +#define NRF24_CMD_R_RX_PL_WID 0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO. +#define NRF24_CMD_W_ACK_PAYLOAD 0xA8 // [1010 1PPP] Write ACK Payload to be with ACK packet on PIPE PPP +#define NRF24_CMD_W_TX_PAYLOAD_NOACK 0xB0 //Write TX payload and disable AUTOACK +#define NRF24_CMD_NOP 0xFF // No operation (used for reading status register) + +#define NRF24_CMD_ACTIVATE 0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features +#define NRF24_CMD_LOCK_UNLOCK 0x50 // Lock/unlock exclusive features + +// SPI(nRF24L01) register address definitions +#define NRF24_REG_CONFIG 0x00 // Configuration register +#define NRF24_REG_EN_AA 0x01 // Enable "Auto acknowledgment" +#define NRF24_REG_EN_RXADDR 0x02 // Enable RX addresses +#define NRF24_REG_SETUP_AW 0x03 // Setup of address widths +#define NRF24_REG_SETUP_RETR 0x04 // Setup of automatic re-transmit +#define NRF24_REG_RF_CH 0x05 // RF channel +#define NRF24_REG_RF_SETUP 0x06 // RF setup +#define NRF24_REG_STATUS 0x07 // Status register +#define NRF24_REG_OBSERVE_TX 0x08 // Transmit observe register +#define NRF24_REG_RPD 0x09 // Received power detector +#define NRF24_REG_RX_ADDR_P0 0x0A // Receive address data pipe 0 +#define NRF24_REG_RX_ADDR_P1 0x0B // Receive address data pipe 1 +#define NRF24_REG_RX_ADDR_P2 0x0C // Receive address data pipe 2 +#define NRF24_REG_RX_ADDR_P3 0x0D // Receive address data pipe 3 +#define NRF24_REG_RX_ADDR_P4 0x0E // Receive address data pipe 4 +#define NRF24_REG_RX_ADDR_P5 0x0F // Receive address data pipe 5 +#define NRF24_REG_TX_ADDR 0x10 // Transmit address +#define NRF24_REG_RX_PW_P0 0x11 // Number of bytes in RX payload in data pipe 0 +#define NRF24_REG_RX_PW_P1 0x12 // Number of bytes in RX payload in data pipe 1 +#define NRF24_REG_RX_PW_P2 0x13 // Number of bytes in RX payload in data pipe 2 +#define NRF24_REG_RX_PW_P3 0x14 // Number of bytes in RX payload in data pipe 3 +#define NRF24_REG_RX_PW_P4 0x15 // Number of bytes in RX payload in data pipe 4 +#define NRF24_REG_RX_PW_P5 0x16 // Number of bytes in RX payload in data pipe 5 +#define NRF24_REG_FIFO_STATUS 0x17 // FIFO status register +#define NRF24_REG_DYNPD 0x1C // Enable dynamic payload length +#define NRF24_REG_FEATURE 0x1D // Feature register + +// Register bits definitions +#define NRF24_CONFIG_PRIM_RX 0x01 // PRIM_RX bit in CONFIG register +#define NRF24_CONFIG_PWR_UP 0x02 // PWR_UP bit in CONFIG register +#define NRF24_FEATURE_EN_DYN_ACK 0x01 // EN_DYN_ACK bit in FEATURE register +#define NRF24_FEATURE_EN_ACK_PAY 0x02 // EN_ACK_PAY bit in FEATURE register +#define NRF24_FEATURE_EN_DPL 0x04 // EN_DPL bit in FEATURE register +#define NRF24_FLAG_RX_DREADY 0x40 // RX_DR bit (data ready RX FIFO interrupt) +#define NRF24_FLAG_TX_DSENT 0x20 // TX_DS bit (data sent TX FIFO interrupt) +#define NRF24_FLAG_MAX_RT 0x10 // MAX_RT bit (maximum number of TX re-transmits interrupt) +#define NRF24_FLAG_TX_FULL 0x01 // 1:TX FIFO full + +// Register masks definitions +#define NRF24_MASK_REG_MAP 0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands +#define NRF24_MASK_CRC 0x0C // Mask for CRC bits [3:2] in CONFIG register +#define NRF24_MASK_STATUS_IRQ 0x70 // Mask for all IRQ bits in STATUS register +#define NRF24_MASK_RF_PWR 0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register +#define NRF24_MASK_RX_P_NO 0x0E // Mask RX_P_NO[3:1] bits in STATUS register +#define NRF24_MASK_DATARATE 0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register +#define NRF24_MASK_EN_RX 0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register +#define NRF24_MASK_RX_PW 0x3F // Mask [5:0] bits in RX_PW_Px register +#define NRF24_MASK_RETR_ARD 0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register +#define NRF24_MASK_RETR_ARC 0x0F // Mask for ARC[3:0] bits in SETUP_RETR register +#define NRF24_MASK_RXFIFO 0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register +#define NRF24_MASK_TXFIFO 0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register +#define NRF24_MASK_PLOS_CNT 0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register +#define NRF24_MASK_ARC_CNT 0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register + +#define NRF24_ADDR_WIDTH 5 // RX/TX address width +#define NRF24_PLOAD_WIDTH 32 // Payload width +#define NRF24_TEST_ADDR "nRF24" + +typedef enum +{ + NRF24_MODE_RX = 0x00, + NRF24_MODE_TX = 0x01 +} NRF24_MODE; + +typedef enum +{ + NRF24_SCEN_RX = 0x00, + NRF24_SCEN_TX = 0x01, + NRF24_SCEN_HALF_DUPLEX = 0x02 +} NRF24_SCEN; + + +void NRF24L01_WriteReg(uint8_t reg, uint8_t value); + +uint8_t NRF24L01_ReadReg(uint8_t reg); + +void NRF24L01_ReadToBuf(uint8_t reg, uint8_t *pBuf, uint8_t len); + +void NRF24L01_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len); + +void NRF24L01_PrintBuf(uint8_t *buf); + +/** +* Flush the RX FIFO +*/ +void NRF24L01_FlushRX(void); + +/** +* Flush the TX FIFO +*/ +void NRF24L01_FlushTX(void); + +void NRF24L01_CheckFlag(uint8_t *tx_ds, uint8_t *max_rt, uint8_t *rx_dr); +uint8_t NRF24L01_RxAvailable(uint8_t* pipe_num); + +void NRF24L01_HandelIrqFlag(uint8_t *buf); +void NRF24L01_Tx(uint8_t *txbuf); +void NRF24L01_StartFastWrite(const void* txbuf); +uint8_t NRF24L01_WriteFast(const void* txbuf); +void NRF24L01_ResetTX(void); +uint8_t NRF24L01_Check(void); +void NRF24L01_Init(NRF24_MODE mode); + + +#endif \ No newline at end of file diff --git a/demo/spi/nrf24l01/nrf24l01_stc8h3k.c b/demo/spi/nrf24l01/nrf24l01_stc8h3k.c new file mode 100644 index 0000000..441bbcf --- /dev/null +++ b/demo/spi/nrf24l01/nrf24l01_stc8h3k.c @@ -0,0 +1,151 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * Example code of SPI driving NRF24L01 module + * + * Pin connection: + * P35(SS, Ignored) => CSN + * P34(MOSI) => MOSI + * P33(MISO) => MISO + * P32(SPCLK) => CLK + * P36(INT2) => IRQ + * P37(IO) => CE + * + * test-board: Minimum System; test-MCU: STC8H3K32S2 + */ + +#include "nrf24l01.h" +#include + +const NRF24_SCEN CURRENT_SCEN = NRF24_SCEN_HALF_DUPLEX; +extern uint8_t __IDATA xbuf[NRF24_PLOAD_WIDTH + 1]; + +void SPI_Init(void) +{ + // ST7567 doesn't work if SPI frequency is too high + SPI_SetClockPrescaler(SPI_ClockPreScaler_16); + // Clock idles low + SPI_SetClockPolarity(HAL_State_OFF); + // Data transfer is driven by lower SS pin + SPI_SetClockPhase(SPI_ClockPhase_LeadingEdge); + // MSB first + SPI_SetDataOrder(SPI_DataOrder_MSB); + // Define the output pins + SPI_SetPort(SPI_AlterPort_P35_P34_P33_P32); + // Ignore SS pin, use MSTR to swith between master/slave mode + SPI_IgnoreSlaveSelect(HAL_State_ON); + // Master mode + SPI_SetMasterMode(HAL_State_ON); + // Start SPI + SPI_SetEnableState(HAL_State_ON); +} + +void GPIO_Init(void) +{ + // Configure GPIO pins before SPI and device + // MISO(P33) MOSI(P34) + GPIO_P3_SetMode(GPIO_Pin_4, GPIO_Mode_InOut_QBD); + // SCLK(P32) CSN(P35) CE(P37) + GPIO_P3_SetMode(GPIO_Pin_2|GPIO_Pin_5|GPIO_Pin_7, GPIO_Mode_Output_PP); + // IRQ(P36) + GPIO_P3_SetMode(GPIO_Pin_6, GPIO_Mode_Input_HIP); +} + +void INT_Init() +{ + EXTI_Int2_SetIntState(HAL_State_ON); + EXTI_Global_SetIntState(HAL_State_ON); +} + +INTERRUPT(Int2_Routine, EXTI_VectInt2) +{ + NRF24L01_HandelIrqFlag(xbuf); +} + +void main(void) +{ + uint8_t __CODE tmp[] = { + 0x1F, 0x80, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, + 0x21, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x28, + 0x31, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x38, + 0x41, 0x12, 0x13, 0x14, 0x15, 0x16, 0x37, 0x48}; + uint8_t succ = 0, err = 0; + + SYS_SetClock(); + + GPIO_Init(); + // UART1, baud 115200, baud source Timer1, 1T mode, no interrupt + UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer1, HAL_State_ON, 115200); + UART1_TxString("UART Initialized\r\n"); + + SPI_Init(); + UART1_TxString("SPI Initialized\r\n"); + + while (NRF24L01_Check() == 1) + { + UART1_TxString("Check failed\r\n"); + SYS_Delay(1000); + } + UART1_TxString("NRF24L01 Checked\r\n"); + + switch (CURRENT_SCEN) + { + case NRF24_SCEN_TX: + NRF24L01_Init(NRF24_MODE_TX); + UART1_TxString("NRF24L01 Initialized\r\n"); + while (1) + { + if (NRF24L01_WriteFast(tmp) == 0) + { + NRF24L01_ResetTX(); + err++; + } + else + { + succ++; + } + if (err >= 255 || succ >= 255) + { + UART1_TxHex(err); + UART1_TxHex(succ); + UART1_TxChar('.'); + err = 0; + succ = 0; + } + SYS_Delay(50); + } + break; + + case NRF24_SCEN_RX: + NRF24L01_Init(NRF24_MODE_RX); + INT_Init(); + while (1); + break; + + case NRF24_SCEN_HALF_DUPLEX: + NRF24L01_Init(NRF24_MODE_RX); + INT_Init(); + while (1) + { + NRF24L01_Tx(tmp); + SYS_Delay(1000); + } + break; + + default: + UART1_TxString("Unknown scen\r\n"); + break; + } +} \ No newline at end of file diff --git a/demo/spi/st7567/st7567.h b/demo/spi/st7567/st7567.h index 63ea89a..1f6ae98 100644 --- a/demo/spi/st7567/st7567.h +++ b/demo/spi/st7567/st7567.h @@ -12,8 +12,8 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef __ST7567_H_ -#define __ST7567_H_ +#ifndef __FW_ST7567__ +#define __FW_ST7567__ #include "fw_hal.h" diff --git a/include/fw_exti.h b/include/fw_exti.h index eeecfa1..cd60dea 100644 --- a/include/fw_exti.h +++ b/include/fw_exti.h @@ -122,12 +122,9 @@ typedef enum #define EXTI_SPI_SetIntState(__STATE__) SFR_ASSIGN(IE2, 1, __STATE__) #define EXTI_UART2_SetIntState(__STATE__) SFR_ASSIGN(IE2, 0, __STATE__) -#define EXTI_INT_Int4_ON SFR_SET(INTCLKO, 6) -#define EXTI_INT_Int4_OFF SFR_RESET(INTCLKO, 6) -#define EXTI_INT_Int3_ON SFR_SET(INTCLKO, 5) -#define EXTI_INT_Int3_OFF SFR_RESET(INTCLKO, 5) -#define EXTI_INT_Int2_ON SFR_SET(INTCLKO, 4) -#define EXTI_INT_Int2_OFF SFR_RESET(INTCLKO, 4) +#define EXTI_Int4_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 6, __STATE__) +#define EXTI_Int3_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 5, __STATE__) +#define EXTI_Int2_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 4, __STATE__) #define EXTI_INT_CompRise_ON SFR_SET(CMPCR1, 5) #define EXTI_INT_CompRise_OFF SFR_RESET(CMPCR1, 5) diff --git a/include/fw_reg_base.h b/include/fw_reg_base.h index d106df2..51fd46b 100644 --- a/include/fw_reg_base.h +++ b/include/fw_reg_base.h @@ -12,8 +12,8 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef __IO_REG_BASE_H__ -#define __IO_REG_BASE_H__ +#ifndef __FW_REG_BASE_H__ +#define __FW_REG_BASE_H__ #if defined (SDCC) || defined (__SDCC) diff --git a/include/fw_reg_stc8g.h b/include/fw_reg_stc8g.h index 2670a38..1311c8d 100644 --- a/include/fw_reg_stc8g.h +++ b/include/fw_reg_stc8g.h @@ -1,5 +1,5 @@ -#ifndef __IO_REG_STC8G_H__ -#define __IO_REG_STC8G_H__ +#ifndef __FW_REG_STC8G_H__ +#define __FW_REG_STC8G_H__ #include "fw_reg_base.h" diff --git a/include/fw_reg_stc8h.h b/include/fw_reg_stc8h.h index 4e32e4d..8154fe2 100644 --- a/include/fw_reg_stc8h.h +++ b/include/fw_reg_stc8h.h @@ -1,5 +1,5 @@ -#ifndef __IO_REG_STC8H_H__ -#define __IO_REG_STC8H_H__ +#ifndef __FW_REG_STC8H_H__ +#define __FW_REG_STC8H_H__ #include "fw_reg_base.h" diff --git a/include/fw_uart.h b/include/fw_uart.h index 3ae45d0..0a107fb 100644 --- a/include/fw_uart.h +++ b/include/fw_uart.h @@ -21,6 +21,8 @@ #define UART_RX_BUFF_SIZE 0x20 +int16_t UART_Timer_InitValueCalculate(uint32_t sysclk, HAL_State_t _1TMode, uint32_t baudrate); + /**************************************************************************** / * UART1 diff --git a/src/fw_uart.c b/src/fw_uart.c index 4e60caa..3dfafd3 100644 --- a/src/fw_uart.c +++ b/src/fw_uart.c @@ -16,18 +16,13 @@ #include "fw_tim.h" #include "fw_sys.h" -static const char hexTable[16] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'}; -char wptr, rptr, UART1_RxBuffer[UART_RX_BUFF_SIZE]; +__CODE static char hexTable[16] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'}; +__IDATA char wptr, rptr, UART1_RxBuffer[UART_RX_BUFF_SIZE]; __BIT busy; - -/**************************************************************************** / - * UART1 -*/ - -int16_t _UART1_Timer_InitValueCalculate(HAL_State_t _1TMode, uint32_t baudrate) +int16_t UART_Timer_InitValueCalculate(uint32_t sysclk, HAL_State_t _1TMode, uint32_t baudrate) { - uint32_t value, sysclk = SYS_GetSysClock(); + uint32_t value; value = sysclk / (4 * baudrate); if (!_1TMode) value = value / 12; @@ -37,9 +32,12 @@ int16_t _UART1_Timer_InitValueCalculate(HAL_State_t _1TMode, uint32_t baudrate) return 0xFFFF - value + 1; } -void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate) +/**************************************************************************** / + * UART1 +*/ + +void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, int16_t init) { - uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); UART1_SetBaudSource(baudSource); // Timer1 configuration. Mode0 only, mode2 is covered by mode0 so it is unnecessary. if (baudSource == UART1_BaudSource_Timer1) @@ -60,14 +58,22 @@ void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, ui } void UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate) { + uint16_t init; + uint32_t sysclk; SM0=0; SM1=1; - _UART1_ConfigDynUart(baudSource, _1TMode, baudrate); + sysclk = SYS_GetSysClock(); + init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate); + _UART1_ConfigDynUart(baudSource, _1TMode, init); } void UART1_ConfigMode3Dyn9bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate) { + uint16_t init; + uint32_t sysclk; SM0=1; SM1=1; - _UART1_ConfigDynUart(baudSource, _1TMode, baudrate); + sysclk = SYS_GetSysClock(); + init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate); + _UART1_ConfigDynUart(baudSource, _1TMode, init); } void UART1_InterruptHandler(void) @@ -128,7 +134,10 @@ void UART1_TxString(uint8_t *str) void UART2_Config(HAL_State_t _1TMode, uint32_t baudrate) { - uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); + uint16_t init; + uint32_t sysclk; + sysclk = SYS_GetSysClock(); + init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate); // Timer2: 1T mode and initial value. prescaler is ignored, no interrupt. TIM_Timer2_Set1TMode(_1TMode); TIM_Timer2_SetInitValue(init >> 8, init & 0xFF); @@ -161,8 +170,10 @@ void UART2_TxString(uint8_t *str) void UART3_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate) { uint16_t init; + uint32_t sysclk; UART3_SetBaudSource(0x00); - init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); + sysclk = SYS_GetSysClock(); + init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate); // Timer2: 1T mode and initial value. prescaler is ignored, no interrupt. TIM_Timer2_Set1TMode(_1TMode); TIM_Timer2_SetInitValue(init >> 8, init & 0xFF); @@ -172,8 +183,10 @@ void UART3_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate) void UART3_ConfigOnTimer3(HAL_State_t _1TMode, uint32_t baudrate) { uint16_t init; + uint32_t sysclk; UART3_SetBaudSource(0x01); - init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); + sysclk = SYS_GetSysClock(); + init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate); // Timer3: 1T mode and initial value. prescaler is ignored, no interrupt. TIM_Timer3_Set1TMode(_1TMode); TIM_Timer3_SetInitValue(init >> 8, init & 0xFF); @@ -188,8 +201,10 @@ void UART3_ConfigOnTimer3(HAL_State_t _1TMode, uint32_t baudrate) void UART4_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate) { uint16_t init; + uint32_t sysclk; UART4_SetBaudSource(0x00); - init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); + sysclk = SYS_GetSysClock(); + init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate); TIM_Timer2_Set1TMode(_1TMode); TIM_Timer2_SetInitValue(init >> 8, init & 0xFF); TIM_Timer2_SetRunState(HAL_State_ON); @@ -198,8 +213,10 @@ void UART4_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate) void UART4_ConfigOnTimer4(HAL_State_t _1TMode, uint32_t baudrate) { uint16_t init; + uint32_t sysclk; UART4_SetBaudSource(0x01); - init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); + sysclk = SYS_GetSysClock(); + init = UART_Timer_InitValueCalculate(sysclk, _1TMode, baudrate); TIM_Timer4_Set1TMode(_1TMode); TIM_Timer4_SetInitValue(init >> 8, init & 0xFF); TIM_Timer4_SetRunState(HAL_State_ON);