feat: pca for stc8g, chipid for stc8h8k64u
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IOsetting
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demo/mem/mem_read_chipid.c
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92
demo/mem/mem_read_chipid.c
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@ -0,0 +1,92 @@
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// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/**
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* Built-in Readonly CHIPID on following MCU types with firmwaire version >= 7.4.4
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* STC8H8K64U,
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* STC8H4K64LCD,
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* STC8H4K64TLR,
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* STC8H4K64TLCD
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*/
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#include "fw_hal.h"
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uint8_t __XDATA i, buff[32] = {0};
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void main(void)
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{
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SYS_SetClock();
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// UART1 configuration: baud 115200 with Timer2, 1T mode, no interrupt
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UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer2, HAL_State_ON, 115200);
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MEM_ReadChipID(buff);
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for (i = 0; i < 32; i++)
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{
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UART1_TxHex(*(buff + i));
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if (i % 8 == 7) UART1_TxChar(0x20);
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}
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UART1_TxString("\r\n STC8H8K64U ");
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UART1_TxString("\r\nCPUID: ");
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for (i = 0; i < 7; i++)
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{
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UART1_TxHex(*(buff + i));
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}
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UART1_TxString("\r\nVref 1.19V: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n32KHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n22.1184MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n24MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n20MHz 27MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n27MHz 30MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n30MHz 33.1176MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n33.1776MHz 35MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n35MHz 36.864MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n36.864MHz 40MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n40MHz 44.2368MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n45MHz 48MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\nVRTRIM 6MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\nVRTRIM 10MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\nVRTRIM 27MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\nVRTRIM 44MHz: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n00: 0x");
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UART1_TxHex(*(buff + i++));
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UART1_TxString("\r\n\r\n");
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UART1_TxString("Current IRCBAND:");
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UART1_TxHex(IRCBAND);
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UART1_TxString(", VRTRIM:");
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UART1_TxHex(VRTRIM);
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UART1_TxString(", IRTRIM:");
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UART1_TxHex(IRTRIM);
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UART1_TxString(", LIRTRIM:");
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UART1_TxHex(LIRTRIM);
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UART1_TxString("\r\n\r\n");
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while(1);
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}
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@ -36,21 +36,24 @@
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K32T ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLR ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32LCD )
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32LCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K32U )
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#define __CID_ADDR 0x7FE7
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#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S4 ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S2 ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K48T ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLR ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48LCD )
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48LCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K48U )
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#define __CID_ADDR 0xBFE7
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#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S4 ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S2 ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K60T ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLR ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60LCD )
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60LCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K60U )
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#define __CID_ADDR 0xEFE7
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#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S4 ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S2 ) || \
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@ -62,18 +65,22 @@
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#define __CID_ADDR 0xFDE7
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#endif
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#define ID_ROMADDR ( (unsigned char __CODE *)(__CID_ADDR + 15)) // MCU ID 7 bytes
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#define VREF_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 13))
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#define F32K_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 11))
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#define T22M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 10)) //22.1184MHz (20M)
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#define T24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 9)) //24MHz (20M)
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#define T20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 8)) //20MHz (20M)
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#define T27M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 7)) //27MHz (35M)
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#define T30M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 6)) //30MHz (35M)
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#define T33M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 5)) //33.1776MHz (35M)
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#define T35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 4)) //35MHz (35M)
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#define T36M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 3)) //36.864MHz (35M)
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#define VRT20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 1)) //VRTRIM of 20M
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#define VRT35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 0)) //VRTRIM of 35M
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#define ID_ROMADDR ( (unsigned char __CODE *)(__CID_ADDR + 18)) // MCU ID 7 bytes
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#define VREF_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 16)) //1.19Vref
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#define F32K_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 14)) //32kHz frequency
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#define T22M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 13)) //22.1184MHz (20M)
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#define T24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 12)) //24MHz (20M)
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#define T20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 11)) //20MHz (20M)
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#define T27M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 10)) //27MHz (35M)
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#define T30M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 9)) //30MHz (35M)
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#define T33M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 8)) //33.1776MHz (35M)
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#define T35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 7)) //35MHz (35M)
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#define T36M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 6)) //36.864MHz (35M)
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#define T40M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 5)) //
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#define T45M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 4)) //
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#define VRT20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 3)) //VRTRIM of IRCBAND 0
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#define VRT35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 2)) //VRTRIM of IRCBAND 1
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#define VRT24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 1)) //VRTRIM of IRCBAND 2
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#define VRT40M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 0)) //VRTRIM of IRCBAND 3
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#endif
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@ -63,7 +63,11 @@
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#define MCU_MODEL_STC8H4K64TLCD 0x2D
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#define MCU_MODEL_STC8H4K64LCD 0x2E
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#define MCU_MODEL_STC8H8K64U 0x2F
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#define MCU_MODEL_STC8H8K32U 0x2F
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#define MCU_MODEL_STC8H8K48U 0x30
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#define MCU_MODEL_STC8H8K60U 0x31
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#define MCU_MODEL_STC8H8K64U 0x32
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#ifndef __CONF_FOSC
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@ -138,7 +142,10 @@
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLR ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64LCD ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K64U )
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K32U ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K48U ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K60U ) || \
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(__CONF_MCU_MODEL == MCU_MODEL_STC8H8K64U )
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#define __CONF_MCU_TYPE 3
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#endif
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@ -25,7 +25,13 @@
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#include "fw_uart.h"
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#include "fw_adc.h"
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#include "fw_spi.h"
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#include "fw_pwm.h"
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#include "fw_util.h"
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#if (__CONF_MCU_TYPE == 2 )
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#include "fw_pca.h"
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#endif
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#if (__CONF_MCU_TYPE == 3 )
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#include "fw_pwm.h"
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#endif
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#endif
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@ -18,6 +18,10 @@
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#include "fw_conf.h"
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#include "fw_types.h"
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#define MEM_ReadCODE(__ADDR__) (*(unsigned char volatile __CODE *)(__ADDR__))
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// Set P_SW2 = 0x80 before using this macro
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#define MEM_ReadXDATA(__ADDR__) (*(unsigned char volatile __XDATA *)(__ADDR__))
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typedef enum
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{
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MEM_WorkRegGroup_00H_07H = 0x00,
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@ -28,5 +32,6 @@ typedef enum
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void MEM_SelectWorkRegGroup(MEM_WorkRegGroup_t WorkRegGroup);
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void MEM_SetOnchipExtRAM(HAL_State_t HAL_State);
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void MEM_ReadChipID(uint8_t *buff);
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#endif
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121
include/fw_pca.h
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include/fw_pca.h
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// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ___FW_PCA_H___
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#define ___FW_PCA_H___
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#include "fw_conf.h"
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#include "fw_types.h"
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typedef enum
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{
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PCA_ClockSource_SysClkDiv12 = 0x00,
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PCA_ClockSource_SysClkDiv2 = 0x01,
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PCA_ClockSource_Timer0Overflow = 0x02,
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PCA_ClockSource_ExtClock = 0x03,
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PCA_ClockSource_SysClk = 0x04,
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PCA_ClockSource_SysClkDiv4 = 0x05,
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PCA_ClockSource_SysClkDiv6 = 0x06,
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PCA_ClockSource_SysClkDiv8 = 0x07,
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} PCA_ClockSource_t;
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typedef enum
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{
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PCA_WorkMode_None = 0x00, // n/a
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PCA_WorkMode_PWM_NonInterrupt = 0x42, // 6/7/8/10-bit PWM, no interrupt
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PCA_WorkMode_PWM_RiseInterrupt = 0x63, // 6/7/8/10-bit PWM, rising interrupt
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PCA_WorkMode_PWM_FallInterrupt = 0x53, // 6/7/8/10-bit PWM, falling interrupt
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PCA_WorkMode_PWM_EdgeInterrupt = 0x73, // 6/7/8/10-bit PWM, both edge interrupt
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PCA_WorkMode_CAP_16bitRising = 0x20, // 16-bit Capture Mode, capture triggered by rising edge on CCPn/PCAn
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PCA_WorkMode_CAP_16bitFalling = 0x10, // 16-bit Capture Mode, capture triggered by falling edge on CCPn/PCAn
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PCA_WorkMode_CAP_16bitEdge = 0x30, // 16-bit Capture Mode, capture triggered by both edge on CCPn/PCAn
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PCA_WorkMode_CAP_16bitTimer = 0x48, // 16-bit software timer
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PCA_WorkMode_CAP_16bitPulseOut = 0x4C, // 16-bit high-speed pulse output
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} PCA_WorkMode_t;
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typedef enum
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{
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PCA_PWM_BitWidth_8 = 0x00, // {EPCnH, CCAPnH[7:0]} {EPCnL, CCAPnL[7:0]}
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PCA_PWM_BitWidth_7 = 0x01, // {EPCnH, CCAPnH[6:0]} {EPCnL, CCAPnL[6:0]}
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PCA_PWM_BitWidth_6 = 0x02, // {EPCnH, CCAPnH[5:0]} {EPCnL, CCAPnL[5:0]}
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PCA_PWM_BitWidth_10 = 0x03, // {EPCnH, XCCAPnH[1:0], CCAPnH[7:0]} {EPCnL, XCCAPnL[1:0], CCAPnL[7:0]}
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} PCA_PWM_Bitwidth_t;
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typedef enum
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{
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// ECI CCP0 CCP1 CCP2
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PCA_AlterPort_P12_P11_P10_P37 = 0x00,
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PCA_AlterPort_P34_P35_P36_P37 = 0x01,
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PCA_AlterPort_P24_P25_P26_P27 = 0x10,
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} PCA_AlterPort_t;
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typedef enum
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{
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// ECI CCP0 CCP1 CCP2
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PCA_AlterPort_G1K08A_P55_P32_P33_P54 = 0x00,
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PCA_AlterPort_G1K08A_P55_P31_P33_P54 = 0x01,
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PCA_AlterPort_G1K08A_P31_P32_P33_P55 = 0x10,
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} PCA_AlterPort_G1K08A_t;
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typedef enum
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{
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// ECI CCP0 CCP1 CCP2
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PCA_AlterPort_G1K08T_P13_P11_P10_P37 = 0x00,
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PCA_AlterPort_G1K08T_P34_P35_P36_P37 = 0x01,
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PCA_AlterPort_G1K08T_P54_P13_P14_P15 = 0x10,
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} PCA_AlterPort_G1K08T_t;
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#define PCA_SetCounterState(__STATE__) SBIT_ASSIGN(CR, __STATE__)
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#define PCA_ClearCounterOverflowInterrupt() SBIT_RESET(CF)
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#define PCA_PCA0_ClearInterrupt() SBIT_RESET(CCF0)
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#define PCA_PCA1_ClearInterrupt() SBIT_RESET(CCF1)
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#define PCA_PCA2_ClearInterrupt() SBIT_RESET(CCF2)
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#define PCA_SetStopCounterInIdle(__STATE__) SFR_ASSIGN(CMOD, 7, __STATE__)
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#define PCA_SetClockSource(__SOURCE___) (CMOD = CMOD & ~(0x07 << 1) | ((__SOURCE___) << 1))
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#define PCA_EnableCounterOverflowInterrupt(__STATE__) SFR_ASSIGN(CMOD, 0, __STATE__)
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#define PCA_PCA0_SetMode(__MODE__) (CCAPM0 = (__MODE__))
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#define PCA_PCA1_SetMode(__MODE__) (CCAPM1 = (__MODE__))
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#define PCA_PCA2_SetMode(__MODE__) (CCAPM2 = (__MODE__))
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#define PCA_PWM0_SetBitWidth(__BIT_WIDTH__) (PCA_PWM0 = PCA_PWM0 & ~(0x03 << 6) | ((__BIT_WIDTH__) << 6))
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#define PCA_PWM1_SetBitWidth(__BIT_WIDTH__) (PCA_PWM1 = PCA_PWM1 & ~(0x03 << 6) | ((__BIT_WIDTH__) << 6))
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#define PCA_PWM2_SetBitWidth(__BIT_WIDTH__) (PCA_PWM2 = PCA_PWM2 & ~(0x03 << 6) | ((__BIT_WIDTH__) << 6))
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// TODO: set high 8-bit should be enough
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#define PCA_PCA0_SetCompareValue(__VALUE__) do{CCAP0H = (__VALUE__); CCAP0L = (__VALUE__);}while(0)
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#define PCA_PCA1_SetCompareValue(__VALUE__) do{CCAP1H = (__VALUE__); CCAP1L = (__VALUE__);}while(0)
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#define PCA_PCA2_SetCompareValue(__VALUE__) do{CCAP2H = (__VALUE__); CCAP2L = (__VALUE__);}while(0)
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// TODO: set high 8-bit should be enough
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#define PCA_PCA0_SetCompareValue10bit(__VALUE__) do{ \
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CCAP0H = ((__VALUE__) & 0xFF); CCAP0L = ((__VALUE__) & 0xFF); \
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PCA_PWM0 = PCA_PWM0 & ~(0x0F << 2) | (((__VALUE__) >> 4) & 0x30) | (((__VALUE__) >> 6) & 0x0C); \
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}while(0)
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#define PCA_PCA1_SetCompareValue10bit(__VALUE__) do{ \
|
||||
CCAP1H = ((__VALUE__) & 0xFF); CCAP1L = ((__VALUE__) & 0xFF); \
|
||||
PCA_PWM1 = PCA_PWM1 & ~(0x0F << 2) | (((__VALUE__) >> 4) & 0x30) | (((__VALUE__) >> 6) & 0x0C); \
|
||||
}while(0)
|
||||
#define PCA_PCA2_SetCompareValue10bit(__VALUE__) do{ \
|
||||
CCAP2H = ((__VALUE__) & 0xFF); CCAP2L = ((__VALUE__) & 0xFF); \
|
||||
PCA_PWM2 = PCA_PWM2 & ~(0x0F << 2) | (((__VALUE__) >> 4) & 0x30) | (((__VALUE__) >> 6) & 0x0C); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* Alternative port selection
|
||||
*/
|
||||
#define PCA_SetPort(__ALTER_PORT__) (P_SW1 = P_SW1 & ~(0x03 << 4) | ((__ALTER_PORT__) << 4))
|
||||
|
||||
#endif
|
||||
@ -368,6 +368,8 @@ SFR(RSTCFG, 0xFF);
|
||||
#define P7WKUE (*(unsigned char volatile __XDATA *)0xfd47)
|
||||
#define PIN_IP (*(unsigned char volatile __XDATA *)0xfd60)
|
||||
#define PIN_IPH (*(unsigned char volatile __XDATA *)0xfd61)
|
||||
#define CHIPIDxx 0xfde0
|
||||
#define CHIPID00 (*(unsigned char volatile __XDATA *)0xfde0)
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
//FC00H-FCFFH
|
||||
|
||||
10
src/fw_mem.c
10
src/fw_mem.c
@ -23,4 +23,14 @@ void MEM_SelectWorkRegGroup(MEM_WorkRegGroup_t WorkRegGroup)
|
||||
void MEM_SetOnchipExtRAM(HAL_State_t HAL_State)
|
||||
{
|
||||
AUXR = AUXR & ~B00000010 | (HAL_State << 1);
|
||||
}
|
||||
|
||||
void MEM_ReadChipID(uint8_t *buff)
|
||||
{
|
||||
P_SW2 = 0x80;
|
||||
for (uint8_t i = 0; i < 32; i++)
|
||||
{
|
||||
*(buff + i) = MEM_ReadXDATA(CHIPIDxx + i);
|
||||
}
|
||||
P_SW2 = 0x00;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user