diff --git a/demo/mem/mem_read_chipid.c b/demo/mem/mem_read_chipid.c new file mode 100644 index 0000000..1a314e5 --- /dev/null +++ b/demo/mem/mem_read_chipid.c @@ -0,0 +1,92 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * Built-in Readonly CHIPID on following MCU types with firmwaire version >= 7.4.4 + * STC8H8K64U, + * STC8H4K64LCD, + * STC8H4K64TLR, + * STC8H4K64TLCD +*/ +#include "fw_hal.h" + +uint8_t __XDATA i, buff[32] = {0}; + +void main(void) +{ + SYS_SetClock(); + // UART1 configuration: baud 115200 with Timer2, 1T mode, no interrupt + UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer2, HAL_State_ON, 115200); + + MEM_ReadChipID(buff); + for (i = 0; i < 32; i++) + { + UART1_TxHex(*(buff + i)); + if (i % 8 == 7) UART1_TxChar(0x20); + } + UART1_TxString("\r\n STC8H8K64U "); + UART1_TxString("\r\nCPUID: "); + for (i = 0; i < 7; i++) + { + UART1_TxHex(*(buff + i)); + } + UART1_TxString("\r\nVref 1.19V: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n32KHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n22.1184MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n24MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n20MHz 27MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n27MHz 30MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n30MHz 33.1176MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n33.1776MHz 35MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n35MHz 36.864MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n36.864MHz 40MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n40MHz 44.2368MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n45MHz 48MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\nVRTRIM 6MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\nVRTRIM 10MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\nVRTRIM 27MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\nVRTRIM 44MHz: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n00: 0x"); + UART1_TxHex(*(buff + i++)); + UART1_TxString("\r\n\r\n"); + UART1_TxString("Current IRCBAND:"); + UART1_TxHex(IRCBAND); + UART1_TxString(", VRTRIM:"); + UART1_TxHex(VRTRIM); + UART1_TxString(", IRTRIM:"); + UART1_TxHex(IRTRIM); + UART1_TxString(", LIRTRIM:"); + UART1_TxHex(LIRTRIM); + UART1_TxString("\r\n\r\n"); + + while(1); +} \ No newline at end of file diff --git a/include/fw_cid_stc8h.h b/include/fw_cid_stc8h.h index 4cd27d0..fd25d77 100644 --- a/include/fw_cid_stc8h.h +++ b/include/fw_cid_stc8h.h @@ -36,21 +36,24 @@ (__CONF_MCU_MODEL == MCU_MODEL_STC8H2K32T ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLR ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLCD ) || \ - (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32LCD ) + (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32LCD ) || \ + (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K32U ) #define __CID_ADDR 0x7FE7 #elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S4 ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S2 ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H2K48T ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLR ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLCD ) || \ - (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48LCD ) + (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48LCD ) || \ + (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K48U ) #define __CID_ADDR 0xBFE7 #elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S4 ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S2 ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H2K60T ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLR ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLCD ) || \ - (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60LCD ) + (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60LCD ) || \ + (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K60U ) #define __CID_ADDR 0xEFE7 #elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S4 ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S2 ) || \ @@ -62,18 +65,22 @@ #define __CID_ADDR 0xFDE7 #endif -#define ID_ROMADDR ( (unsigned char __CODE *)(__CID_ADDR + 15)) // MCU ID 7 bytes -#define VREF_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 13)) -#define F32K_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 11)) -#define T22M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 10)) //22.1184MHz (20M) -#define T24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 9)) //24MHz (20M) -#define T20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 8)) //20MHz (20M) -#define T27M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 7)) //27MHz (35M) -#define T30M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 6)) //30MHz (35M) -#define T33M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 5)) //33.1776MHz (35M) -#define T35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 4)) //35MHz (35M) -#define T36M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 3)) //36.864MHz (35M) -#define VRT20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 1)) //VRTRIM of 20M -#define VRT35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 0)) //VRTRIM of 35M +#define ID_ROMADDR ( (unsigned char __CODE *)(__CID_ADDR + 18)) // MCU ID 7 bytes +#define VREF_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 16)) //1.19Vref +#define F32K_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 14)) //32kHz frequency +#define T22M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 13)) //22.1184MHz (20M) +#define T24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 12)) //24MHz (20M) +#define T20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 11)) //20MHz (20M) +#define T27M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 10)) //27MHz (35M) +#define T30M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 9)) //30MHz (35M) +#define T33M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 8)) //33.1776MHz (35M) +#define T35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 7)) //35MHz (35M) +#define T36M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 6)) //36.864MHz (35M) +#define T40M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 5)) // +#define T45M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 4)) // +#define VRT20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 3)) //VRTRIM of IRCBAND 0 +#define VRT35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 2)) //VRTRIM of IRCBAND 1 +#define VRT24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 1)) //VRTRIM of IRCBAND 2 +#define VRT40M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 0)) //VRTRIM of IRCBAND 3 #endif diff --git a/include/fw_conf.h b/include/fw_conf.h index 090f007..0d4239a 100644 --- a/include/fw_conf.h +++ b/include/fw_conf.h @@ -63,7 +63,11 @@ #define MCU_MODEL_STC8H4K64TLCD 0x2D #define MCU_MODEL_STC8H4K64LCD 0x2E -#define MCU_MODEL_STC8H8K64U 0x2F +#define MCU_MODEL_STC8H8K32U 0x2F +#define MCU_MODEL_STC8H8K48U 0x30 +#define MCU_MODEL_STC8H8K60U 0x31 +#define MCU_MODEL_STC8H8K64U 0x32 + #ifndef __CONF_FOSC @@ -138,7 +142,10 @@ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLR ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLCD ) || \ (__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64LCD ) || \ - (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K64U ) + (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K32U ) || \ + (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K48U ) || \ + (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K60U ) || \ + (__CONF_MCU_MODEL == MCU_MODEL_STC8H8K64U ) #define __CONF_MCU_TYPE 3 #endif diff --git a/include/fw_hal.h b/include/fw_hal.h index 4dd2a43..3e5694c 100644 --- a/include/fw_hal.h +++ b/include/fw_hal.h @@ -25,7 +25,13 @@ #include "fw_uart.h" #include "fw_adc.h" #include "fw_spi.h" -#include "fw_pwm.h" #include "fw_util.h" +#if (__CONF_MCU_TYPE == 2 ) +#include "fw_pca.h" +#endif +#if (__CONF_MCU_TYPE == 3 ) +#include "fw_pwm.h" +#endif + #endif diff --git a/include/fw_mem.h b/include/fw_mem.h index 0912553..3847eb4 100644 --- a/include/fw_mem.h +++ b/include/fw_mem.h @@ -18,6 +18,10 @@ #include "fw_conf.h" #include "fw_types.h" +#define MEM_ReadCODE(__ADDR__) (*(unsigned char volatile __CODE *)(__ADDR__)) +// Set P_SW2 = 0x80 before using this macro +#define MEM_ReadXDATA(__ADDR__) (*(unsigned char volatile __XDATA *)(__ADDR__)) + typedef enum { MEM_WorkRegGroup_00H_07H = 0x00, @@ -28,5 +32,6 @@ typedef enum void MEM_SelectWorkRegGroup(MEM_WorkRegGroup_t WorkRegGroup); void MEM_SetOnchipExtRAM(HAL_State_t HAL_State); +void MEM_ReadChipID(uint8_t *buff); #endif diff --git a/include/fw_pca.h b/include/fw_pca.h new file mode 100644 index 0000000..92c6b4c --- /dev/null +++ b/include/fw_pca.h @@ -0,0 +1,121 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef ___FW_PCA_H___ +#define ___FW_PCA_H___ + +#include "fw_conf.h" +#include "fw_types.h" + +typedef enum +{ + PCA_ClockSource_SysClkDiv12 = 0x00, + PCA_ClockSource_SysClkDiv2 = 0x01, + PCA_ClockSource_Timer0Overflow = 0x02, + PCA_ClockSource_ExtClock = 0x03, + PCA_ClockSource_SysClk = 0x04, + PCA_ClockSource_SysClkDiv4 = 0x05, + PCA_ClockSource_SysClkDiv6 = 0x06, + PCA_ClockSource_SysClkDiv8 = 0x07, +} PCA_ClockSource_t; + +typedef enum +{ + PCA_WorkMode_None = 0x00, // n/a + PCA_WorkMode_PWM_NonInterrupt = 0x42, // 6/7/8/10-bit PWM, no interrupt + PCA_WorkMode_PWM_RiseInterrupt = 0x63, // 6/7/8/10-bit PWM, rising interrupt + PCA_WorkMode_PWM_FallInterrupt = 0x53, // 6/7/8/10-bit PWM, falling interrupt + PCA_WorkMode_PWM_EdgeInterrupt = 0x73, // 6/7/8/10-bit PWM, both edge interrupt + PCA_WorkMode_CAP_16bitRising = 0x20, // 16-bit Capture Mode, capture triggered by rising edge on CCPn/PCAn + PCA_WorkMode_CAP_16bitFalling = 0x10, // 16-bit Capture Mode, capture triggered by falling edge on CCPn/PCAn + PCA_WorkMode_CAP_16bitEdge = 0x30, // 16-bit Capture Mode, capture triggered by both edge on CCPn/PCAn + PCA_WorkMode_CAP_16bitTimer = 0x48, // 16-bit software timer + PCA_WorkMode_CAP_16bitPulseOut = 0x4C, // 16-bit high-speed pulse output +} PCA_WorkMode_t; + +typedef enum +{ + PCA_PWM_BitWidth_8 = 0x00, // {EPCnH, CCAPnH[7:0]} {EPCnL, CCAPnL[7:0]} + PCA_PWM_BitWidth_7 = 0x01, // {EPCnH, CCAPnH[6:0]} {EPCnL, CCAPnL[6:0]} + PCA_PWM_BitWidth_6 = 0x02, // {EPCnH, CCAPnH[5:0]} {EPCnL, CCAPnL[5:0]} + PCA_PWM_BitWidth_10 = 0x03, // {EPCnH, XCCAPnH[1:0], CCAPnH[7:0]} {EPCnL, XCCAPnL[1:0], CCAPnL[7:0]} +} PCA_PWM_Bitwidth_t; + +typedef enum +{ + // ECI CCP0 CCP1 CCP2 + PCA_AlterPort_P12_P11_P10_P37 = 0x00, + PCA_AlterPort_P34_P35_P36_P37 = 0x01, + PCA_AlterPort_P24_P25_P26_P27 = 0x10, +} PCA_AlterPort_t; + +typedef enum +{ + // ECI CCP0 CCP1 CCP2 + PCA_AlterPort_G1K08A_P55_P32_P33_P54 = 0x00, + PCA_AlterPort_G1K08A_P55_P31_P33_P54 = 0x01, + PCA_AlterPort_G1K08A_P31_P32_P33_P55 = 0x10, +} PCA_AlterPort_G1K08A_t; + +typedef enum +{ + // ECI CCP0 CCP1 CCP2 + PCA_AlterPort_G1K08T_P13_P11_P10_P37 = 0x00, + PCA_AlterPort_G1K08T_P34_P35_P36_P37 = 0x01, + PCA_AlterPort_G1K08T_P54_P13_P14_P15 = 0x10, +} PCA_AlterPort_G1K08T_t; + + +#define PCA_SetCounterState(__STATE__) SBIT_ASSIGN(CR, __STATE__) +#define PCA_ClearCounterOverflowInterrupt() SBIT_RESET(CF) +#define PCA_PCA0_ClearInterrupt() SBIT_RESET(CCF0) +#define PCA_PCA1_ClearInterrupt() SBIT_RESET(CCF1) +#define PCA_PCA2_ClearInterrupt() SBIT_RESET(CCF2) + +#define PCA_SetStopCounterInIdle(__STATE__) SFR_ASSIGN(CMOD, 7, __STATE__) +#define PCA_SetClockSource(__SOURCE___) (CMOD = CMOD & ~(0x07 << 1) | ((__SOURCE___) << 1)) +#define PCA_EnableCounterOverflowInterrupt(__STATE__) SFR_ASSIGN(CMOD, 0, __STATE__) + +#define PCA_PCA0_SetMode(__MODE__) (CCAPM0 = (__MODE__)) +#define PCA_PCA1_SetMode(__MODE__) (CCAPM1 = (__MODE__)) +#define PCA_PCA2_SetMode(__MODE__) (CCAPM2 = (__MODE__)) + +#define PCA_PWM0_SetBitWidth(__BIT_WIDTH__) (PCA_PWM0 = PCA_PWM0 & ~(0x03 << 6) | ((__BIT_WIDTH__) << 6)) +#define PCA_PWM1_SetBitWidth(__BIT_WIDTH__) (PCA_PWM1 = PCA_PWM1 & ~(0x03 << 6) | ((__BIT_WIDTH__) << 6)) +#define PCA_PWM2_SetBitWidth(__BIT_WIDTH__) (PCA_PWM2 = PCA_PWM2 & ~(0x03 << 6) | ((__BIT_WIDTH__) << 6)) + +// TODO: set high 8-bit should be enough +#define PCA_PCA0_SetCompareValue(__VALUE__) do{CCAP0H = (__VALUE__); CCAP0L = (__VALUE__);}while(0) +#define PCA_PCA1_SetCompareValue(__VALUE__) do{CCAP1H = (__VALUE__); CCAP1L = (__VALUE__);}while(0) +#define PCA_PCA2_SetCompareValue(__VALUE__) do{CCAP2H = (__VALUE__); CCAP2L = (__VALUE__);}while(0) +// TODO: set high 8-bit should be enough +#define PCA_PCA0_SetCompareValue10bit(__VALUE__) do{ \ + CCAP0H = ((__VALUE__) & 0xFF); CCAP0L = ((__VALUE__) & 0xFF); \ + PCA_PWM0 = PCA_PWM0 & ~(0x0F << 2) | (((__VALUE__) >> 4) & 0x30) | (((__VALUE__) >> 6) & 0x0C); \ + }while(0) +#define PCA_PCA1_SetCompareValue10bit(__VALUE__) do{ \ + CCAP1H = ((__VALUE__) & 0xFF); CCAP1L = ((__VALUE__) & 0xFF); \ + PCA_PWM1 = PCA_PWM1 & ~(0x0F << 2) | (((__VALUE__) >> 4) & 0x30) | (((__VALUE__) >> 6) & 0x0C); \ + }while(0) +#define PCA_PCA2_SetCompareValue10bit(__VALUE__) do{ \ + CCAP2H = ((__VALUE__) & 0xFF); CCAP2L = ((__VALUE__) & 0xFF); \ + PCA_PWM2 = PCA_PWM2 & ~(0x0F << 2) | (((__VALUE__) >> 4) & 0x30) | (((__VALUE__) >> 6) & 0x0C); \ + }while(0) + +/** + * Alternative port selection +*/ +#define PCA_SetPort(__ALTER_PORT__) (P_SW1 = P_SW1 & ~(0x03 << 4) | ((__ALTER_PORT__) << 4)) + +#endif diff --git a/include/fw_reg_stc8h.h b/include/fw_reg_stc8h.h index 934a7bb..4e32e4d 100644 --- a/include/fw_reg_stc8h.h +++ b/include/fw_reg_stc8h.h @@ -368,6 +368,8 @@ SFR(RSTCFG, 0xFF); #define P7WKUE (*(unsigned char volatile __XDATA *)0xfd47) #define PIN_IP (*(unsigned char volatile __XDATA *)0xfd60) #define PIN_IPH (*(unsigned char volatile __XDATA *)0xfd61) +#define CHIPIDxx 0xfde0 +#define CHIPID00 (*(unsigned char volatile __XDATA *)0xfde0) ///////////////////////////////////////////////// //FC00H-FCFFH diff --git a/src/fw_mem.c b/src/fw_mem.c index 01e80b5..f40702c 100644 --- a/src/fw_mem.c +++ b/src/fw_mem.c @@ -23,4 +23,14 @@ void MEM_SelectWorkRegGroup(MEM_WorkRegGroup_t WorkRegGroup) void MEM_SetOnchipExtRAM(HAL_State_t HAL_State) { AUXR = AUXR & ~B00000010 | (HAL_State << 1); +} + +void MEM_ReadChipID(uint8_t *buff) +{ + P_SW2 = 0x80; + for (uint8_t i = 0; i < 32; i++) + { + *(buff + i) = MEM_ReadXDATA(CHIPIDxx + i); + } + P_SW2 = 0x00; } \ No newline at end of file