frist commit
This commit is contained in:
IOsetting
commit
595bacdd18
0
.gitignore
vendored
Normal file
0
.gitignore
vendored
Normal file
110
demo/tim/timer0_print_cpuid.c
Normal file
110
demo/tim/timer0_print_cpuid.c
Normal file
@ -0,0 +1,110 @@
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#include "fw_hal.h"
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static uint16_t counter = 0;
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uint8_t readCode(uint8_t offset)
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{
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return (*(unsigned char volatile __CODE *)(__CID_ADDR + offset));
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}
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INTERRUPT(Timer0_Routine, EXTI_VectTimer0)
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{
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uint8_t i, j;
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counter++;
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if (counter == 1000)
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{
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i = 0;
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counter = 0;
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UART1_TxString("ADDR: 0x");
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UART1_TxHex(__CID_ADDR >> 8);
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UART1_TxHex(__CID_ADDR & 0xFF);
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UART1_TxString("\r\n");
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UART1_TxString(" VER1 VER2\r\n");
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UART1_TxString("VRTRIM 40M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("VRTRIM 24M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("VRTRIM 35M ??M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("VRTRIM 20M ??M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM --- 45M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM --- 40M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 36.864M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 35M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 33.1776M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 30M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 27M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 20M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 24M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("ITRIM 22.1184M: ");
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("32kHz PD FreQ: ");
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UART1_TxHex(readCode(i++));
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("1.19Vref: ");
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UART1_TxHex(readCode(i++));
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UART1_TxHex(readCode(i++));
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UART1_TxString("\r\n");
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UART1_TxString("\r\n");
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UART1_TxString("MCUID: ");
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for (j = 0; j < 7; j++)
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{
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UART1_TxHex(readCode(i+j));
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UART1_TxChar(' ');
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}
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UART1_TxString("\r\n");
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UART1_TxString("Current IRCBAND:");
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UART1_TxHex(IRCBAND);
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UART1_TxString(", VRTRIM:");
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UART1_TxHex(VRTRIM);
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UART1_TxString(", IRTRIM:");
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UART1_TxHex(IRTRIM);
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UART1_TxString(", LIRTRIM:");
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UART1_TxHex(LIRTRIM);
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UART1_TxString("\r\n\r\n");
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}
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}
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void main(void)
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{
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SYS_Init();
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// UART1 configuration: baud 115200 with Timer2, 1T mode, no interrupt
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UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer2, HAL_State_ON, 115200, HAL_State_OFF);
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// Timer0 configuration: 1T mode, 16-bit auto-reload, frequency 1000, interrupt enabled
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TIM_Timer0_Config(
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HAL_State_ON,
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TIM_TimerMode_16BitAuto,
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1000,
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HAL_State_ON,
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EXTI_IntPriority_High);
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TIM_Timer0_SetRunState(HAL_State_ON);
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EXTI_Global_SetIntState(HAL_State_ON);
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while(1);
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}
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30
demo/tim/timer0_timer_1t.c
Normal file
30
demo/tim/timer0_timer_1t.c
Normal file
@ -0,0 +1,30 @@
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#include "fw_hal.h"
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static uint16_t counter = 0;
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INTERRUPT(Timer0_Routine, EXTI_VectTimer0)
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{
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counter++;
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if (counter == 1000)
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{
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counter = 0;
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UART1_TxString("hello\r\n");
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}
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}
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void main(void)
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{
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SYS_Init();
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// UART1 configuration: baud 115200 with Timer1, 1T mode, no interrupt
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UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer1, HAL_State_ON, 115200, HAL_State_OFF);
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EXTI_Global_SetIntState(HAL_State_ON);
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TIM_Timer0_Config(
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HAL_State_ON,
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TIM_TimerMode_16BitAuto,
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1000,
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HAL_State_ON,
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EXTI_IntPriority_High);
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TIM_Timer0_SetRunState(HAL_State_ON);
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while(1);
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}
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21
demo/tim/timer2_timer_12t.c
Normal file
21
demo/tim/timer2_timer_12t.c
Normal file
@ -0,0 +1,21 @@
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#include "fw_hal.h"
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static uint8_t counter = 0;
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INTERRUPT(Timer2_Routine, EXTI_VectTimer2)
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{
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UART1_TxString("hello\r\n");
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}
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void main(void)
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{
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SYS_Init();
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// UART1 configuration: baud 115200 with Timer1, 1T mode, no interrupt
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UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer1, HAL_State_ON, 115200, HAL_State_OFF);
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EXTI_Global_SetIntState(HAL_State_ON);
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// 12T mode, prescaler:255+1, frequency: 1, interrupt: ON
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TIM_Timer2_Config(HAL_State_OFF, 0xFF, 1, HAL_State_ON);
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TIM_Timer2_SetRunState(HAL_State_ON);
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while(1);
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}
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26
demo/tim/timer2_timer_1t.c
Normal file
26
demo/tim/timer2_timer_1t.c
Normal file
@ -0,0 +1,26 @@
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#include "fw_hal.h"
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static uint8_t counter = 0;
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INTERRUPT(Timer2_Routine, EXTI_VectTimer2)
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{
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counter++;
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if (counter == 5)
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{
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counter = 0;
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UART1_TxString("hello\r\n");
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}
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}
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void main(void)
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{
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SYS_Init();
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// UART1 configuration: baud 115200 with Timer1, 1T mode, no interrupt
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UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer1, HAL_State_ON, 115200, HAL_State_OFF);
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EXTI_Global_SetIntState(HAL_State_ON);
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// 1T mode, prescaler:255+1, frequency: 5, interrupt: ON
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TIM_Timer2_Config(HAL_State_ON, 0xFF, 5, HAL_State_ON);
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TIM_Timer2_SetRunState(HAL_State_ON);
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while(1);
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}
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27
demo/uart/uart1_int_tx_rx.c
Normal file
27
demo/uart/uart1_int_tx_rx.c
Normal file
@ -0,0 +1,27 @@
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#include "fw_hal.h"
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extern char UART1_RxBuffer[UART_RX_BUFF_SIZE];
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INTERRUPT(UART1_Routine, EXTI_VectUART1)
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{
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UART1_InterruptHandler();
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}
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void main(void)
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{
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SYS_Init();
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UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer2, HAL_State_ON, 115200, HAL_State_ON);
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UART1_SetRxState(HAL_State_ON);
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while(1)
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{
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UART1_IntTxChar('R');
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UART1_IntTxChar('X');
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UART1_IntTxChar(':');
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for (uint8_t i = 0; i < UART_RX_BUFF_SIZE; i++) UART1_IntTxChar(UART1_RxBuffer[i]);
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UART1_IntTxChar(' ');
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UART1_IntTxHex(0x41);
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UART1_IntTxHex('A');
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UART1_IntTxString(" string\r\n");
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SYS_Delay(1000);
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}
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}
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15
demo/uart/uart1_tx.c
Normal file
15
demo/uart/uart1_tx.c
Normal file
@ -0,0 +1,15 @@
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#include "fw_hal.h"
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|
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||||||
|
void main(void)
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||||||
|
{
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||||||
|
SYS_Init();
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||||||
|
UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer2, HAL_State_ON, 115200, HAL_State_OFF);
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||||||
|
while(1)
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||||||
|
{
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||||||
|
UART1_TxChar('T');
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||||||
|
UART1_TxHex(0x41);
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||||||
|
UART1_TxString("U");
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||||||
|
UART1_TxString(" string\r\n");
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||||||
|
SYS_Delay(1000);
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||||||
|
}
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||||||
|
}
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||||||
15
demo/uart/uart2_tx.c
Normal file
15
demo/uart/uart2_tx.c
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
#include "fw_hal.h"
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||||||
|
|
||||||
|
void main(void)
|
||||||
|
{
|
||||||
|
SYS_Init();
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||||||
|
UART2_ConfigMode0Dyn8bitUart(HAL_State_ON, 115200, HAL_State_OFF);
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
UART2_TxChar('T');
|
||||||
|
UART2_TxHex(0x41);
|
||||||
|
UART2_TxString("U");
|
||||||
|
UART2_TxString(" string\r\n");
|
||||||
|
SYS_Delay(1000);
|
||||||
|
}
|
||||||
|
}
|
||||||
41
include/fw_cid_stc8g.h
Normal file
41
include/fw_cid_stc8g.h
Normal file
@ -0,0 +1,41 @@
|
|||||||
|
#ifndef __FW_CID_STC8G_H__
|
||||||
|
#define __FW_CID_STC8G_H__
|
||||||
|
|
||||||
|
#include "fw_reg_base.h"
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CONF_MCU_MODEL == MCU_MODEL_STC8G1K04 )
|
||||||
|
#define __CID_ADDR 0x0FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G1K08 )
|
||||||
|
#define __CID_ADDR 0x1FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G1K12 )
|
||||||
|
#define __CID_ADDR 0x2FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G2K16 )
|
||||||
|
#define __CID_ADDR 0x3FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G1K17 )
|
||||||
|
#define __CID_ADDR 0x43E9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G2K32 )
|
||||||
|
#define __CID_ADDR 0x7FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G2K48 )
|
||||||
|
#define __CID_ADDR 0xBFE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G2K60 )
|
||||||
|
#define __CID_ADDR 0xEFE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G2K64 )
|
||||||
|
#define __CID_ADDR 0xFDE9
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define ID_ROMADDR ( (unsigned char __CODE *)(__CID_ADDR + 15)) // MCU ID 7 bytes
|
||||||
|
#define VREF_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 13))
|
||||||
|
#define F32K_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 11))
|
||||||
|
#define T22M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 10)) //22.1184MHz (20M)
|
||||||
|
#define T24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 9)) //24MHz (20M)
|
||||||
|
#define T20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 8)) //20MHz (20M)
|
||||||
|
#define T27M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 7)) //27MHz (35M)
|
||||||
|
#define T30M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 6)) //30MHz (35M)
|
||||||
|
#define T33M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 5)) //33.1776MHz (35M)
|
||||||
|
#define T35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 4)) //35MHz (35M)
|
||||||
|
#define T36M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 3)) //36.864MHz (35M)
|
||||||
|
#define VRT20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 1)) //VRTRIM of 20M
|
||||||
|
#define VRT35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 0)) //VRTRIM of 35M
|
||||||
|
|
||||||
|
#endif
|
||||||
64
include/fw_cid_stc8h.h
Normal file
64
include/fw_cid_stc8h.h
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
#ifndef __FW_CID_STC8H_H__
|
||||||
|
#define __FW_CID_STC8H_H__
|
||||||
|
|
||||||
|
#include "fw_reg_base.h"
|
||||||
|
|
||||||
|
#if (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K08 )
|
||||||
|
#define __CID_ADDR 0x1FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K12 )
|
||||||
|
#define __CID_ADDR 0x2FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K16 )
|
||||||
|
#define __CID_ADDR 0x3FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K17 )
|
||||||
|
#define __CID_ADDR 0x43E9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K24 )
|
||||||
|
#define __CID_ADDR 0x5FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K28 )
|
||||||
|
#define __CID_ADDR 0x6FE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K33 )
|
||||||
|
#define __CID_ADDR 0x83E9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K32S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K32S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K32T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32LCD )
|
||||||
|
#define __CID_ADDR 0x7FE7
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K48T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48LCD )
|
||||||
|
#define __CID_ADDR 0xBFE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K60T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60LCD )
|
||||||
|
#define __CID_ADDR 0xEFE9
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K64T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64LCD )
|
||||||
|
#define __CID_ADDR 0xFDE9
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define ID_ROMADDR ( (unsigned char __CODE *)(__CID_ADDR + 15)) // MCU ID 7 bytes
|
||||||
|
#define VREF_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 13))
|
||||||
|
#define F32K_ROMADDR (*(unsigned int __CODE *)(__CID_ADDR + 11))
|
||||||
|
#define T22M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 10)) //22.1184MHz (20M)
|
||||||
|
#define T24M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 9)) //24MHz (20M)
|
||||||
|
#define T20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 8)) //20MHz (20M)
|
||||||
|
#define T27M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 7)) //27MHz (35M)
|
||||||
|
#define T30M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 6)) //30MHz (35M)
|
||||||
|
#define T33M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 5)) //33.1776MHz (35M)
|
||||||
|
#define T35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 4)) //35MHz (35M)
|
||||||
|
#define T36M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 3)) //36.864MHz (35M)
|
||||||
|
#define VRT20M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 1)) //VRTRIM of 20M
|
||||||
|
#define VRT35M_ROMADDR (*(unsigned char __CODE *)(__CID_ADDR + 0)) //VRTRIM of 35M
|
||||||
|
|
||||||
|
#endif
|
||||||
125
include/fw_conf.h
Normal file
125
include/fw_conf.h
Normal file
@ -0,0 +1,125 @@
|
|||||||
|
#ifndef ___FW_CONF_H___
|
||||||
|
#define ___FW_CONF_H___
|
||||||
|
|
||||||
|
#define MCU_MODEL_STC8A8K64D4 0x01
|
||||||
|
|
||||||
|
#define MCU_MODEL_STC8G1K04 0x02
|
||||||
|
#define MCU_MODEL_STC8G1K08 0x03
|
||||||
|
#define MCU_MODEL_STC8G1K12 0x04
|
||||||
|
#define MCU_MODEL_STC8G1K17 0x05
|
||||||
|
#define MCU_MODEL_STC8G2K16 0x06
|
||||||
|
#define MCU_MODEL_STC8G2K32 0x07
|
||||||
|
#define MCU_MODEL_STC8G2K48 0x08
|
||||||
|
#define MCU_MODEL_STC8G2K60 0x09
|
||||||
|
#define MCU_MODEL_STC8G2K64 0x0a
|
||||||
|
|
||||||
|
#define MCU_MODEL_STC8H1K08 0x10
|
||||||
|
#define MCU_MODEL_STC8H1K12 0x11
|
||||||
|
#define MCU_MODEL_STC8H1K16 0x12
|
||||||
|
#define MCU_MODEL_STC8H1K17 0x13
|
||||||
|
#define MCU_MODEL_STC8H1K24 0x14
|
||||||
|
#define MCU_MODEL_STC8H1K28 0x15
|
||||||
|
#define MCU_MODEL_STC8H1K33 0x16
|
||||||
|
|
||||||
|
#define MCU_MODEL_STC8H3K32S4 0x17
|
||||||
|
#define MCU_MODEL_STC8H3K32S2 0x18
|
||||||
|
#define MCU_MODEL_STC8H2K32T 0x19
|
||||||
|
#define MCU_MODEL_STC8H4K32TLR 0x1A
|
||||||
|
#define MCU_MODEL_STC8H4K32TLCD 0x1B
|
||||||
|
#define MCU_MODEL_STC8H4K32LCD 0x1C
|
||||||
|
|
||||||
|
#define MCU_MODEL_STC8H3K48S4 0x1D
|
||||||
|
#define MCU_MODEL_STC8H3K48S2 0x1E
|
||||||
|
#define MCU_MODEL_STC8H2K48T 0x1F
|
||||||
|
#define MCU_MODEL_STC8H4K48TLR 0x20
|
||||||
|
#define MCU_MODEL_STC8H4K48TLCD 0x21
|
||||||
|
#define MCU_MODEL_STC8H4K48LCD 0x22
|
||||||
|
|
||||||
|
#define MCU_MODEL_STC8H3K60S4 0x23
|
||||||
|
#define MCU_MODEL_STC8H3K60S2 0x24
|
||||||
|
#define MCU_MODEL_STC8H2K60T 0x25
|
||||||
|
#define MCU_MODEL_STC8H4K60TLR 0x26
|
||||||
|
#define MCU_MODEL_STC8H4K60TLCD 0x27
|
||||||
|
#define MCU_MODEL_STC8H4K60LCD 0x28
|
||||||
|
|
||||||
|
#define MCU_MODEL_STC8H3K64S4 0x29
|
||||||
|
#define MCU_MODEL_STC8H3K64S2 0x2A
|
||||||
|
#define MCU_MODEL_STC8H2K64T 0x2B
|
||||||
|
#define MCU_MODEL_STC8H4K64TLR 0x2C
|
||||||
|
#define MCU_MODEL_STC8H4K64TLCD 0x2D
|
||||||
|
#define MCU_MODEL_STC8H4K64LCD 0x2E
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CONF_FOSC
|
||||||
|
#define __CONF_FOSC 24000000UL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CONF_IRCBAND
|
||||||
|
#define __CONF_IRCBAND 0x00
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CONF_VRTRIM
|
||||||
|
#define __CONF_VRTRIM 0x20
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CONF_IRTRIM
|
||||||
|
#define __CONF_IRTRIM 0xC8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CONF_LIRTRIM
|
||||||
|
#define __CONF_LIRTRIM 0x00
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CONF_MCU_MODEL
|
||||||
|
#define __CONF_MCU_MODEL MCU_MODEL_STC8H1K08
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (__CONF_MCU_MODEL == MCU_MODEL_STC8A8K64D4)
|
||||||
|
#include "fw_reg_stc8a.h"
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8G1K04 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G1K08 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G1K12 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G1K17 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G2K16 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G2K32 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G2K48 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G2K60 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8G2K64 )
|
||||||
|
#include "fw_reg_stc8g.h"
|
||||||
|
#include "fw_cid_stc8g.h"
|
||||||
|
#elif (__CONF_MCU_MODEL == MCU_MODEL_STC8H1K08 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H1K12 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H1K16 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H1K17 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H1K24 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H1K28 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H1K33 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K32S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K32S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K32T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K32LCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K48S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K48T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K48LCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K60S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K60T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K60LCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S4 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H3K64S2 ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H2K64T ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLR ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64TLCD ) || \
|
||||||
|
(__CONF_MCU_MODEL == MCU_MODEL_STC8H4K64LCD )
|
||||||
|
#include "fw_reg_stc8h.h"
|
||||||
|
#include "fw_cid_stc8h.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
160
include/fw_exti.h
Normal file
160
include/fw_exti.h
Normal file
@ -0,0 +1,160 @@
|
|||||||
|
#ifndef ___FW_EXTI_H___
|
||||||
|
#define ___FW_EXTI_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_IntPriority_Lowest = 0x00,
|
||||||
|
EXTI_IntPriority_Low = 0x01,
|
||||||
|
EXTI_IntPriority_High = 0x02,
|
||||||
|
EXTI_IntPriority_Highest = 0x03,
|
||||||
|
} EXTI_IntPriority_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_PortIntMode_Fall = 0x00,
|
||||||
|
EXTI_PortIntMode_Rise = 0x01,
|
||||||
|
EXTI_PortIntMode_Low = 0x02,
|
||||||
|
EXTI_PortIntMode_High = 0x03,
|
||||||
|
} EXTI_PortIntMode_t;
|
||||||
|
|
||||||
|
#define EXTI_VectInt0 0
|
||||||
|
#define EXTI_VectTimer0 1
|
||||||
|
#define EXTI_VectInt1 2
|
||||||
|
#define EXTI_VectTimer1 3
|
||||||
|
#define EXTI_VectUART1 4
|
||||||
|
#define EXTI_VectADC 5
|
||||||
|
#define EXTI_VectLowVoltDect 6
|
||||||
|
#define EXTI_VectPCA 7
|
||||||
|
#define EXTI_VectUART2 8
|
||||||
|
#define EXTI_VectSPI 9
|
||||||
|
#define EXTI_VectInt2 10
|
||||||
|
#define EXTI_VectInt3 11
|
||||||
|
#define EXTI_VectTimer2 12
|
||||||
|
#define EXTI_VectInt4 16
|
||||||
|
#define EXTI_VectUART3 17
|
||||||
|
#define EXTI_VectUART4 18
|
||||||
|
#define EXTI_VectTimer3 19
|
||||||
|
#define EXTI_VectTimer4 20
|
||||||
|
#define EXTI_VectCMP 21
|
||||||
|
#define EXTI_VectPWM 22
|
||||||
|
#define EXTI_VectPWMFD 23
|
||||||
|
#define EXTI_VectI2C 24
|
||||||
|
|
||||||
|
#define EXTI_Global_SetIntState(__STATE__) SBIT_ASSIGN(EA, __STATE__)
|
||||||
|
#define EXTI_Timer0_SetIntState(__STATE__) SBIT_ASSIGN(ET0, __STATE__)
|
||||||
|
#define EXTI_Timer1_SetIntState(__STATE__) SBIT_ASSIGN(ET1, __STATE__)
|
||||||
|
#define EXTI_ADC_SetIntState(__STATE__) SBIT_ASSIGN(EADC, __STATE__)
|
||||||
|
#define EXTI_UART1_SetIntState(__STATE__) SBIT_ASSIGN(ES, __STATE__)
|
||||||
|
#define EXTI_LowVoltDetect_SetIntState(__STATE__) SBIT_ASSIGN(ELVD, __STATE__)
|
||||||
|
#define EXTI_Int0_SetIntState(__STATE__) SBIT_ASSIGN(EX0, __STATE__)
|
||||||
|
#define EXTI_Int1_SetIntState(__STATE__) SBIT_ASSIGN(EX1, __STATE__)
|
||||||
|
|
||||||
|
#define EXTI_Int0_SetTrigByFall SBIT_SET(IT0) // Trigger by falling
|
||||||
|
#define EXTI_Int0_SetTrigByBoth SBIT_RESET(IT0) // Trigger by both rising and falling
|
||||||
|
#define EXTI_Int1_SetTrigByFall SBIT_SET(IT1) // Trigger by falling
|
||||||
|
#define EXTI_Int1_SetTrigByBoth SBIT_RESET(IT1) // Trigger by both rising and falling
|
||||||
|
|
||||||
|
#define EXTI_USB_SetIntState(__STATE__) SFR_ASSIGN(IE2, 7, __STATE__)
|
||||||
|
#define EXTI_Timer4_SetIntState(__STATE__) SFR_ASSIGN(IE2, 6, __STATE__)
|
||||||
|
#define EXTI_Timer3_SetIntState(__STATE__) SFR_ASSIGN(IE2, 5, __STATE__)
|
||||||
|
#define EXTI_UART4_SetIntState(__STATE__) SFR_ASSIGN(IE2, 4, __STATE__)
|
||||||
|
#define EXTI_UART3_SetIntState(__STATE__) SFR_ASSIGN(IE2, 3, __STATE__)
|
||||||
|
#define EXTI_Timer2_SetIntState(__STATE__) SFR_ASSIGN(IE2, 2, __STATE__)
|
||||||
|
#define EXTI_SPI_SetIntState(__STATE__) SFR_ASSIGN(IE2, 1, __STATE__)
|
||||||
|
#define EXTI_UART2_SetIntState(__STATE__) SFR_ASSIGN(IE2, 0, __STATE__)
|
||||||
|
|
||||||
|
#define EXTI_INT_Int4_ON SFR_SET(INTCLKO, 6)
|
||||||
|
#define EXTI_INT_Int4_OFF SFR_RESET(INTCLKO, 6)
|
||||||
|
#define EXTI_INT_Int3_ON SFR_SET(INTCLKO, 5)
|
||||||
|
#define EXTI_INT_Int3_OFF SFR_RESET(INTCLKO, 5)
|
||||||
|
#define EXTI_INT_Int2_ON SFR_SET(INTCLKO, 4)
|
||||||
|
#define EXTI_INT_Int2_OFF SFR_RESET(INTCLKO, 4)
|
||||||
|
|
||||||
|
#define EXTI_INT_CompRise_ON SFR_SET(CMPCR1, 5)
|
||||||
|
#define EXTI_INT_CompRise_OFF SFR_RESET(CMPCR1, 5)
|
||||||
|
#define EXTI_INT_CompFall_ON SFR_SET(CMPCR1, 4)
|
||||||
|
#define EXTI_INT_CompFall_OFF SFR_RESET(CMPCR1, 4)
|
||||||
|
|
||||||
|
#define EXTI_INT_I2cMaster_ON SFRX_SET(I2CMSCR, 7)
|
||||||
|
#define EXTI_INT_I2cMaster_OFF SFRX_RESET(I2CMSCR, 7)
|
||||||
|
#define EXTI_INT_I2cSlvRxStart_ON SFRX_SET(I2CSLCR, 6)
|
||||||
|
#define EXTI_INT_I2cSlvRxStart_OFF SFRX_RESET(I2CSLCR, 6)
|
||||||
|
#define EXTI_INT_I2cSlvRxEnd_ON SFRX_SET(I2CSLCR, 5)
|
||||||
|
#define EXTI_INT_I2cSlvRxEnd_OFF SFRX_RESET(I2CSLCR, 5)
|
||||||
|
#define EXTI_INT_I2cSlvTxEnd_ON SFRX_SET(I2CSLCR, 4)
|
||||||
|
#define EXTI_INT_I2cSlvTxEnd_OFF SFRX_RESET(I2CSLCR, 4)
|
||||||
|
#define EXTI_INT_I2cSlvRxStop_ON SFRX_SET(I2CSLCR, 3)
|
||||||
|
#define EXTI_INT_I2cSlvRxStop_OFF SFRX_RESET(I2CSLCR, 3)
|
||||||
|
|
||||||
|
#define EXTI_INT_PWM1_Break_ON SFRX_SET(PWM1_IER, 7)
|
||||||
|
#define EXTI_INT_PWM1_Break_OFF SFRX_RESET(PWM1_IER, 7)
|
||||||
|
#define EXTI_INT_PWM1_Int_ON SFRX_SET(PWM1_IER, 6)
|
||||||
|
#define EXTI_INT_PWM1_Int_OFF SFRX_RESET(PWM1_IER, 6)
|
||||||
|
#define EXTI_INT_PWM1_Comp_ON SFRX_SET(PWM1_IER, 5)
|
||||||
|
#define EXTI_INT_PWM1_Comp_OFF SFRX_RESET(PWM1_IER, 5)
|
||||||
|
#define EXTI_INT_PWM1_CapCH4_ON SFRX_SET(PWM1_IER, 4)
|
||||||
|
#define EXTI_INT_PWM1_CapCH4_OFF SFRX_RESET(PWM1_IER, 4)
|
||||||
|
#define EXTI_INT_PWM1_CapCH3_ON SFRX_SET(PWM1_IER, 3)
|
||||||
|
#define EXTI_INT_PWM1_CapCH3_OFF SFRX_RESET(PWM1_IER, 3)
|
||||||
|
#define EXTI_INT_PWM1_CapCH2_ON SFRX_SET(PWM1_IER, 2)
|
||||||
|
#define EXTI_INT_PWM1_CapCH2_OFF SFRX_RESET(PWM1_IER, 2)
|
||||||
|
#define EXTI_INT_PWM1_CapCH1_OFF SFRX_SET(PWM1_IER, 1)
|
||||||
|
#define EXTI_INT_PWM1_CapCH1_ON SFRX_RESET(PWM1_IER, 1)
|
||||||
|
#define EXTI_INT_PWM1_Update_OFF SFRX_SET(PWM1_IER, 0)
|
||||||
|
#define EXTI_INT_PWM1_Update_ON SFRX_RESET(PWM1_IER, 0)
|
||||||
|
|
||||||
|
#define EXTI_INT_PWM2_Break_ON SFRX_SET(PWM2_IER, 7)
|
||||||
|
#define EXTI_INT_PWM2_Break_OFF SFRX_RESET(PWM2_IER, 7)
|
||||||
|
#define EXTI_INT_PWM2_Int_ON SFRX_SET(PWM2_IER, 6)
|
||||||
|
#define EXTI_INT_PWM2_Int_OFF SFRX_RESET(PWM2_IER, 6)
|
||||||
|
#define EXTI_INT_PWM2_Comp_ON SFRX_SET(PWM2_IER, 5)
|
||||||
|
#define EXTI_INT_PWM2_Comp_OFF SFRX_RESET(PWM2_IER, 5)
|
||||||
|
#define EXTI_INT_PWM2_CapCH4_ON SFRX_SET(PWM2_IER, 4)
|
||||||
|
#define EXTI_INT_PWM2_CapCH4_OFF SFRX_RESET(PWM2_IER, 4)
|
||||||
|
#define EXTI_INT_PWM2_CapCH3_ON SFRX_SET(PWM2_IER, 3)
|
||||||
|
#define EXTI_INT_PWM2_CapCH3_OFF SFRX_RESET(PWM2_IER, 3)
|
||||||
|
#define EXTI_INT_PWM2_CapCH2_ON SFRX_SET(PWM2_IER, 2)
|
||||||
|
#define EXTI_INT_PWM2_CapCH2_OFF SFRX_RESET(PWM2_IER, 2)
|
||||||
|
#define EXTI_INT_PWM2_CapCH1_OFF SFRX_SET(PWM2_IER, 1)
|
||||||
|
#define EXTI_INT_PWM2_CapCH1_ON SFRX_RESET(PWM2_IER, 1)
|
||||||
|
#define EXTI_INT_PWM2_Update_OFF SFRX_SET(PWM2_IER, 0)
|
||||||
|
#define EXTI_INT_PWM2_Update_ON SFRX_RESET(PWM2_IER, 0)
|
||||||
|
|
||||||
|
#define EXTI_INT_LCM_ON SFRX_SET(LCMIFCFG, 7)
|
||||||
|
#define EXTI_INT_LCM_OFF SFRX_RESET(LCMIFCFG, 7)
|
||||||
|
|
||||||
|
#define EXTI_Port_SetInterrupt_ON(__PORT__, __PINS__) do {P_SW2 = 0x80; SFRX(PxINTE + (__PORT__)) |= (__PINS__); P_SW2 = 0x00;} while(0)
|
||||||
|
#define EXTI_Port_SetInterrupt_OFF(__PORT__, __PINS__) do {P_SW2 = 0x80; SFRX(PxINTE + (__PORT__)) &= ~(__PINS__); P_SW2 = 0x00;} while(0)
|
||||||
|
|
||||||
|
#define EXTI_Int0_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP, IPH, 0, __PRIORITY__)
|
||||||
|
#define EXTI_Timer0_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP, IPH, 1, __PRIORITY__)
|
||||||
|
#define EXTI_Int1_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP, IPH, 2, __PRIORITY__)
|
||||||
|
#define EXTI_Timer1_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP, IPH, 3, __PRIORITY__)
|
||||||
|
#define EXTI_UART1_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP, IPH, 4, __PRIORITY__)
|
||||||
|
#define EXTI_ADC_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP, IPH, 5, __PRIORITY__)
|
||||||
|
#define EXTI_LowVoltDetect_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP, IPH, 6, __PRIORITY__)
|
||||||
|
|
||||||
|
#define EXTI_UART2_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 0, __PRIORITY__)
|
||||||
|
#define EXTI_SPI_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 1, __PRIORITY__)
|
||||||
|
#define EXTI_PWM1_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 2, __PRIORITY__)
|
||||||
|
#define EXTI_PWM2_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 3, __PRIORITY__)
|
||||||
|
#define EXTI_Int4_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 4, __PRIORITY__)
|
||||||
|
#define EXTI_CMP_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 5, __PRIORITY__)
|
||||||
|
#define EXTI_I2c_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 6, __PRIORITY__)
|
||||||
|
#define EXTI_USB_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 7, __PRIORITY__)
|
||||||
|
|
||||||
|
#define EXTI_UART3_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP3, IP3H, 0, __PRIORITY__)
|
||||||
|
#define EXTI_UART4_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP3, IP3H, 1, __PRIORITY__)
|
||||||
|
#define EXTI_RTC_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP3, IP3H, 2, __PRIORITY__)
|
||||||
|
|
||||||
|
#define EXTI_Port_SetIntPriority(__PORT__, __PRIORITY__) SFRX_DUAL_SET(PIN_IP, PIN_IPH, __PORT__, __PRIORITY__)
|
||||||
|
|
||||||
|
#define EXTI_Port_SetIntMode(__PORT__, __PINS__, __PORT_INT_MODE__) do { P_SW2 = 0x80; \
|
||||||
|
SFRX(PxIM0 + (__PORT__)) = SFRX(PxIM0 + (__PORT__)) & ~(__PINS__) | (((__PORT_INT_MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
SFRX(PxIM1 + (__PORT__)) = SFRX(PxIM1 + (__PORT__)) & ~(__PINS__) | (((__PORT_INT_MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
P_SW2 = 0x00; } while(0)
|
||||||
|
|
||||||
|
#endif
|
||||||
134
include/fw_gpio.h
Normal file
134
include/fw_gpio.h
Normal file
@ -0,0 +1,134 @@
|
|||||||
|
#ifndef ___FW_GPIO_H___
|
||||||
|
#define ___FW_GPIO_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_Mode_InOut_QBD = 0x00, /* quasi-bidirectional(be compatible with classical 8051 MCUs) */
|
||||||
|
GPIO_Mode_Output_PP = 0x01, /* push-pull output */
|
||||||
|
GPIO_Mode_Input_HIP = 0x02, /* high-impedance state */
|
||||||
|
GPIO_Mode_Output_OD = 0x03, /* open drain output */
|
||||||
|
} GPIO_Mode_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_Port_0 = 0U,
|
||||||
|
GPIO_Port_1 = 1U,
|
||||||
|
GPIO_Port_2 = 2U,
|
||||||
|
GPIO_Port_3 = 3U,
|
||||||
|
GPIO_Port_4 = 4U,
|
||||||
|
GPIO_Port_5 = 5U,
|
||||||
|
GPIO_Port_6 = 6U,
|
||||||
|
GPIO_Port_7 = 7U,
|
||||||
|
} GPIO_Port_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_Pin_0 = B00000001,
|
||||||
|
GPIO_Pin_1 = B00000010,
|
||||||
|
GPIO_Pin_2 = B00000100,
|
||||||
|
GPIO_Pin_3 = B00001000,
|
||||||
|
GPIO_Pin_4 = B00010000,
|
||||||
|
GPIO_Pin_5 = B00100000,
|
||||||
|
GPIO_Pin_6 = B01000000,
|
||||||
|
GPIO_Pin_7 = B10000000,
|
||||||
|
GPIO_Pin_All = B11111111,
|
||||||
|
} GPIO_Pin_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_SchmittTrigger_ON = 0x00,
|
||||||
|
GPIO_SchmittTrigger_OFF = 0x01,
|
||||||
|
} GPIO_SchmittTrigger_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_SwitchSpeed_High = 0x00,
|
||||||
|
GPIO_SwitchSpeed_Low = 0x01,
|
||||||
|
} GPIO_SwitchSpeed_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_DriveCapability_High = 0x00,
|
||||||
|
GPIO_DriveCapability_Normal = 0x01,
|
||||||
|
} GPIO_DriveCapability_t;
|
||||||
|
|
||||||
|
#define GPIO_P0_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P0M0 = P0M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P0M1 = P0M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_P1_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P1M0 = P1M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P1M1 = P1M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_P2_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P2M0 = P2M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P2M1 = P2M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_P3_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P3M0 = P3M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P3M1 = P3M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_P4_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P4M0 = P4M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P4M1 = P4M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_P5_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P5M0 = P5M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P5M1 = P5M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_P6_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P6M0 = P6M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P6M1 = P6M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_P7_SetMode(__PINS__, __MODE__) do { \
|
||||||
|
P7M0 = P7M0 & ~(__PINS__) | (((__MODE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P7M1 = P7M1 & ~(__PINS__) | (((__MODE__) & 0x02)? (__PINS__) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_SetPullUp(__PORT__, __PINS__, __STATE__) do { \
|
||||||
|
P_SW2 = 0x80; \
|
||||||
|
SFRX(PxPU + (__PORT__)) = SFRX(PxPU + (__PORT__)) \
|
||||||
|
& ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P_SW2 = 0x00; \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_SetSchmittTrigger(__PORT__, __PINS__, __STATE__) do { \
|
||||||
|
P_SW2 = 0x80; \
|
||||||
|
SFRX(PxNCS + (__PORT__)) = SFRX(PxNCS + (__PORT__)) \
|
||||||
|
& ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P_SW2 = 0x00; \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_SetSwitchSpeed(__PORT__, __PINS__, __STATE__) do { \
|
||||||
|
P_SW2 = 0x80; \
|
||||||
|
SFRX(PxSR + (__PORT__)) = SFRX(PxSR + (__PORT__)) \
|
||||||
|
& ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P_SW2 = 0x00; \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_SetDriveCapability(__PORT__, __PINS__, __STATE__) do { \
|
||||||
|
P_SW2 = 0x80; \
|
||||||
|
SFRX(PxDR + (__PORT__)) = SFRX(PxDR + (__PORT__)) \
|
||||||
|
& ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P_SW2 = 0x00; \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#define GPIO_SetDigitalInput(__PORT__, __PINS__, __STATE__) do { \
|
||||||
|
P_SW2 = 0x80; \
|
||||||
|
SFRX(PxIE + (__PORT__)) = SFRX(PxIE + (__PORT__)) \
|
||||||
|
& ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \
|
||||||
|
P_SW2 = 0x00; \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
14
include/fw_hal.h
Normal file
14
include/fw_hal.h
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
#ifndef ___FW_INC_H___
|
||||||
|
#define ___FW_INC_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_sys.h"
|
||||||
|
#include "fw_rcc.h"
|
||||||
|
#include "fw_mem.h"
|
||||||
|
#include "fw_exti.h"
|
||||||
|
#include "fw_gpio.h"
|
||||||
|
#include "fw_tim.h"
|
||||||
|
#include "fw_uart.h"
|
||||||
|
#include "fw_util.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
18
include/fw_mem.h
Normal file
18
include/fw_mem.h
Normal file
@ -0,0 +1,18 @@
|
|||||||
|
#ifndef ___FW_MEM_H___
|
||||||
|
#define ___FW_MEM_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
MEM_WorkRegGroup_00H_07H = 0x00,
|
||||||
|
MEM_WorkRegGroup_08H_0FH = 0x01,
|
||||||
|
MEM_WorkRegGroup_10H_17H = 0x02,
|
||||||
|
MEM_WorkRegGroup_18H_1FH = 0x03,
|
||||||
|
} MEM_WorkRegGroup_t;
|
||||||
|
|
||||||
|
void MEM_SelectWorkRegGroup(MEM_WorkRegGroup_t WorkRegGroup);
|
||||||
|
void MEM_SetOnchipExtRAM(HAL_State_t HAL_State);
|
||||||
|
|
||||||
|
#endif
|
||||||
62
include/fw_rcc.h
Normal file
62
include/fw_rcc.h
Normal file
@ -0,0 +1,62 @@
|
|||||||
|
#ifndef ___FW_RCC_H___
|
||||||
|
#define ___FW_RCC_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RCC_SYSCLKSource_HSI = 0x00, /* Internal high speed RC osc */
|
||||||
|
RCC_SYSCLKSource_HSE = 0x01, /* External high speed osc */
|
||||||
|
RCC_SYSCLKSource_LSE = 0x02, /* External 32KHz osc */
|
||||||
|
RCC_SYSCLKSource_LSI = 0x03, /* Internal 32KHz RC osc */
|
||||||
|
} RCC_SYSCLKSource_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RCC_IRCBand_20MHz = 0x00, /* 20MHz RC osc band */
|
||||||
|
RCC_IRCBand_35MHz = 0x01, /* 35MHz RC osc band */
|
||||||
|
} RCC_IRCBand_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RCC_LIRTrim_None = 0x00, /* none */
|
||||||
|
RCC_LIRTrim_001 = 0x01, /* +0.01% */
|
||||||
|
RCC_LIRTrim_004 = 0x02, /* +0.04% */
|
||||||
|
RCC_LIRTrim_010 = 0x03, /* +0.10% */
|
||||||
|
} RCC_LIRTrim_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RCC_SoftwareReset_Code = 0x00, /* restart from user code */
|
||||||
|
RCC_SoftwareReset_ISP = 0x01, /* restart from ISP */
|
||||||
|
} RCC_SoftwareReset_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RCC_LowVoltResetPinAF_IO = 0x00, /* P5.4 as GPIO */
|
||||||
|
RCC_LowVoltResetPinAF_Reset = 0x01, /* P5.4 as RESET */
|
||||||
|
} RCC_LowVoltResetPinAF_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RCC_LowVoltDetectVolt_2V0 = 0x00, /* Detect at 2.0V */
|
||||||
|
RCC_LowVoltDetectVolt_2V4 = 0x01, /* Detect at 2.4V */
|
||||||
|
RCC_LowVoltDetectVolt_2V7 = 0x02, /* Detect at 2.7V */
|
||||||
|
RCC_LowVoltDetectVolt_3V0 = 0x03, /* Detect at 3.0V */
|
||||||
|
} RCC_LowVoltDetectVolt_t;
|
||||||
|
|
||||||
|
void RCC_SetSYSCLKSource(RCC_SYSCLKSource_t SYSCLKSource);
|
||||||
|
void RCC_SetCLKDivider(uint8_t divider);
|
||||||
|
void RCC_SetIRC(RCC_IRCBand_t IRCBand, uint8_t IRTrim, RCC_LIRTrim_t LIRTrim);
|
||||||
|
void RCC_SoftwareReset(RCC_SoftwareReset_t SoftwareReset);
|
||||||
|
void RCC_ConfigLowVoltReset(
|
||||||
|
HAL_State_t HAL_State,
|
||||||
|
RCC_LowVoltResetPinAF_t LowVoltResetPinAF,
|
||||||
|
RCC_LowVoltDetectVolt_t LowVoltDetectVolt);
|
||||||
|
|
||||||
|
void RCC_SetPowerDownWakeupTimer(HAL_State_t HAL_State, uint16_t countdown);
|
||||||
|
void RCC_SetPowerDownMode(HAL_State_t HAL_State);
|
||||||
|
void RCC_SetIdleMode(HAL_State_t HAL_State);
|
||||||
|
|
||||||
|
#endif
|
||||||
239
include/fw_reg_base.h
Normal file
239
include/fw_reg_base.h
Normal file
@ -0,0 +1,239 @@
|
|||||||
|
#ifndef __IO_REG_BASE_H__
|
||||||
|
#define __IO_REG_BASE_H__
|
||||||
|
|
||||||
|
#if defined (SDCC) || defined (__SDCC)
|
||||||
|
|
||||||
|
#define __IDATA __idata
|
||||||
|
#define __XDATA __xdata
|
||||||
|
#define __CODE __code
|
||||||
|
#define SBIT(name, addr, bit) __sbit __at(addr+bit) name
|
||||||
|
#define SFR(name, addr) __sfr __at(addr) name
|
||||||
|
#define SFRX(addr) (*(unsigned char volatile __xdata *)(addr))
|
||||||
|
#define SFR16X(addr) (*(unsigned int volatile __xdata *)(addr))
|
||||||
|
|
||||||
|
#define INTERRUPT(name, vector) void name (void) __interrupt (vector)
|
||||||
|
#define INTERRUPT_USING(name, vector, regnum) void name (void) __interrupt (vector) __using (regnum)
|
||||||
|
#define NOP() __asm NOP __endasm
|
||||||
|
|
||||||
|
#elif defined __CX51__
|
||||||
|
#define __IDATA idata
|
||||||
|
#define __XDATA xdata
|
||||||
|
#define __CODE code
|
||||||
|
#define SBIT(name, addr, bit) sbit name = addr^bit
|
||||||
|
#define SFR(name, addr) sfr name = addr
|
||||||
|
#define SFRX(addr) (*(unsigned char volatile xdata *)(addr))
|
||||||
|
#define SFR16X(addr) (*(unsigned int volatile xdata *)(addr))
|
||||||
|
|
||||||
|
#define INTERRUPT(name, vector) void name (void) interrupt vector
|
||||||
|
#define INTERRUPT_USING(name, vector, regnum) void name (void) interrupt vector using regnum
|
||||||
|
extern void _nop_ (void);
|
||||||
|
#define NOP() _nop_()
|
||||||
|
|
||||||
|
#else
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <lint.h>
|
||||||
|
# warning unrecognized compiler
|
||||||
|
# define __IDATA
|
||||||
|
# define __XDATA
|
||||||
|
# define __CODE
|
||||||
|
# define SBIT(name, addr, bit) volatile bool name
|
||||||
|
# define SFR(name, addr) volatile unsigned char name
|
||||||
|
# define SFRX(addr) (*(unsigned char volatile *)(addr))
|
||||||
|
# define SFR16X(addr) (*(unsigned char volatile *)(addr))
|
||||||
|
#define INTERRUPT(name, vector) void name (void)
|
||||||
|
#define INTERRUPT_USING(name, vector, regnum) void name (void)
|
||||||
|
#define NOP() ()
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define _P0 0x80
|
||||||
|
SFR(P0, _P0);
|
||||||
|
SBIT(P00, _P0, 0);
|
||||||
|
SBIT(P01, _P0, 1);
|
||||||
|
SBIT(P02, _P0, 2);
|
||||||
|
SBIT(P03, _P0, 3);
|
||||||
|
SBIT(P04, _P0, 4);
|
||||||
|
SBIT(P05, _P0, 5);
|
||||||
|
SBIT(P06, _P0, 6);
|
||||||
|
SBIT(P07, _P0, 7);
|
||||||
|
SFR(SP, 0x81);
|
||||||
|
SFR(DPL, 0x82);
|
||||||
|
SFR(DPH, 0x83);
|
||||||
|
SFR(S4CON, 0x84);
|
||||||
|
SFR(S4BUF, 0x85);
|
||||||
|
SFR(PCON, 0x87);
|
||||||
|
|
||||||
|
#define _TCON 0x88
|
||||||
|
SFR(TCON, _TCON);
|
||||||
|
SBIT(TF1, _TCON, 7);
|
||||||
|
SBIT(TR1, _TCON, 6);
|
||||||
|
SBIT(TF0, _TCON, 5);
|
||||||
|
SBIT(TR0, _TCON, 4);
|
||||||
|
SBIT(IE1, _TCON, 3);
|
||||||
|
SBIT(IT1, _TCON, 2);
|
||||||
|
SBIT(IE0, _TCON, 1);
|
||||||
|
SBIT(IT0, _TCON, 0);
|
||||||
|
SFR(TMOD, 0x89);
|
||||||
|
|
||||||
|
SFR(TL0, 0x8A);
|
||||||
|
SFR(TL1, 0x8B);
|
||||||
|
SFR(TH0, 0x8C);
|
||||||
|
SFR(TH1, 0x8D);
|
||||||
|
SFR(AUXR, 0x8E);
|
||||||
|
SFR(INTCLKO, 0x8F);
|
||||||
|
|
||||||
|
#define _P1 0x90
|
||||||
|
SFR(P1, _P1);
|
||||||
|
SBIT(P10, _P1, 0);
|
||||||
|
SBIT(P11, _P1, 1);
|
||||||
|
SBIT(P12, _P1, 2);
|
||||||
|
SBIT(P13, _P1, 3);
|
||||||
|
SBIT(P14, _P1, 4);
|
||||||
|
SBIT(P15, _P1, 5);
|
||||||
|
SBIT(P16, _P1, 6);
|
||||||
|
SBIT(P17, _P1, 7);
|
||||||
|
SFR(P1M1, 0x91);
|
||||||
|
SFR(P1M0, 0x92);
|
||||||
|
SFR(P0M1, 0x93);
|
||||||
|
SFR(P0M0, 0x94);
|
||||||
|
SFR(P2M1, 0x95);
|
||||||
|
SFR(P2M0, 0x96);
|
||||||
|
|
||||||
|
#define _SCON 0x98
|
||||||
|
SFR(SCON, _SCON);
|
||||||
|
SBIT(SM0, _SCON, 7);
|
||||||
|
SBIT(SM1, _SCON, 6);
|
||||||
|
SBIT(SM2, _SCON, 5);
|
||||||
|
SBIT(REN, _SCON, 4);
|
||||||
|
SBIT(TB8, _SCON, 3);
|
||||||
|
SBIT(RB8, _SCON, 2);
|
||||||
|
SBIT(TI, _SCON, 1);
|
||||||
|
SBIT(RI, _SCON, 0);
|
||||||
|
SFR(SBUF, 0x99);
|
||||||
|
SFR(S2CON, 0x9A);
|
||||||
|
SFR(S2BUF, 0x9B);
|
||||||
|
SFR(IRCBAND, 0x9D);
|
||||||
|
SFR(LIRTRIM, 0x9E);
|
||||||
|
SFR(IRTRIM, 0x9F);
|
||||||
|
|
||||||
|
#define _P2 0xA0
|
||||||
|
SFR(P2, _P2);
|
||||||
|
SBIT(P20, _P2, 0);
|
||||||
|
SBIT(P21, _P2, 1);
|
||||||
|
SBIT(P22, _P2, 2);
|
||||||
|
SBIT(P23, _P2, 3);
|
||||||
|
SBIT(P24, _P2, 4);
|
||||||
|
SBIT(P25, _P2, 5);
|
||||||
|
SBIT(P26, _P2, 6);
|
||||||
|
SBIT(P27, _P2, 7);
|
||||||
|
SFR(P_SW1, 0xA2);
|
||||||
|
SFR(VRTRIM, 0xA6);
|
||||||
|
|
||||||
|
#define _IE 0xA8
|
||||||
|
SFR(IE, _IE);
|
||||||
|
SBIT(EA, _IE, 7);
|
||||||
|
SBIT(ELVD, _IE, 6);
|
||||||
|
SBIT(EADC, _IE, 5);
|
||||||
|
SBIT(ES, _IE, 4);
|
||||||
|
SBIT(ET1, _IE, 3);
|
||||||
|
SBIT(EX1, _IE, 2);
|
||||||
|
SBIT(ET0, _IE, 1);
|
||||||
|
SBIT(EX0, _IE, 0);
|
||||||
|
SFR(SADDR, 0xA9);
|
||||||
|
SFR(WKTCL, 0xAA);
|
||||||
|
SFR(WKTCH, 0xAB);
|
||||||
|
SFR(S3CON, 0xAC);
|
||||||
|
SFR(S3BUF, 0xAD);
|
||||||
|
SFR(TA, 0xAE);
|
||||||
|
SFR(IE2, 0xAF);
|
||||||
|
|
||||||
|
#define _P3 0xB0
|
||||||
|
SFR(P3, _P3);
|
||||||
|
SBIT(P30, _P3, 0);
|
||||||
|
SBIT(P31, _P3, 1);
|
||||||
|
SBIT(P32, _P3, 2);
|
||||||
|
SBIT(P33, _P3, 3);
|
||||||
|
SBIT(P34, _P3, 4);
|
||||||
|
SBIT(P35, _P3, 5);
|
||||||
|
SBIT(P36, _P3, 6);
|
||||||
|
SBIT(P37, _P3, 7);
|
||||||
|
SFR(P3M1, 0xB1);
|
||||||
|
SFR(P3M0, 0xB2);
|
||||||
|
SFR(P4M1, 0xB3);
|
||||||
|
SFR(P4M0, 0xB4);
|
||||||
|
SFR(IP2, 0xB5);
|
||||||
|
SFR(IP2H, 0xB6);
|
||||||
|
SFR(IPH, 0xB7);
|
||||||
|
|
||||||
|
#define _IP 0xB8
|
||||||
|
SFR(IP, _IP);
|
||||||
|
SBIT(PPCA, _IP, 7);
|
||||||
|
SBIT(PLVD, _IP, 6);
|
||||||
|
SBIT(PADC, _IP, 5);
|
||||||
|
SBIT(PS, _IP, 4);
|
||||||
|
SBIT(PT1, _IP, 3);
|
||||||
|
SBIT(PX1, _IP, 2);
|
||||||
|
SBIT(PT0, _IP, 1);
|
||||||
|
SBIT(PX0, _IP, 0);
|
||||||
|
SFR(SADEN, 0xB9);
|
||||||
|
SFR(P_SW2, 0xBA);
|
||||||
|
SFR(ADC_CONTR, 0xBC);
|
||||||
|
SFR(ADC_RES, 0xBD);
|
||||||
|
SFR(ADC_RESL, 0xBE);
|
||||||
|
|
||||||
|
#define _P4 0xC0
|
||||||
|
SFR(P4, _P4);
|
||||||
|
SBIT(P40, _P4, 0);
|
||||||
|
SBIT(P41, _P4, 1);
|
||||||
|
SBIT(P42, _P4, 2);
|
||||||
|
SBIT(P43, _P4, 3);
|
||||||
|
SBIT(P44, _P4, 4);
|
||||||
|
SBIT(P45, _P4, 5);
|
||||||
|
SBIT(P46, _P4, 6);
|
||||||
|
SBIT(P47, _P4, 7);
|
||||||
|
SFR(WDT_CONTR, 0xC1);
|
||||||
|
SFR(IAP_DATA, 0xC2);
|
||||||
|
SFR(IAP_ADDRH, 0xC3);
|
||||||
|
SFR(IAP_ADDRL, 0xC4);
|
||||||
|
SFR(IAP_CMD, 0xC5);
|
||||||
|
SFR(IAP_TRIG, 0xC6);
|
||||||
|
SFR(IAP_CONTR, 0xC7);
|
||||||
|
|
||||||
|
#define _P5 0xC8
|
||||||
|
SFR(P5, _P5);
|
||||||
|
SBIT(P50, _P5, 0);
|
||||||
|
SBIT(P51, _P5, 1);
|
||||||
|
SBIT(P52, _P5, 2);
|
||||||
|
SBIT(P53, _P5, 3);
|
||||||
|
SBIT(P54, _P5, 4);
|
||||||
|
SBIT(P55, _P5, 5);
|
||||||
|
SBIT(P56, _P5, 6);
|
||||||
|
SBIT(P57, _P5, 7);
|
||||||
|
SFR(P5M1, 0xC9);
|
||||||
|
SFR(P5M0, 0xCA);
|
||||||
|
SFR(P6M1, 0xCB);
|
||||||
|
SFR(P6M0, 0xCC);
|
||||||
|
SFR(SPSTAT, 0xCD);
|
||||||
|
SFR(SPCTL, 0xCE);
|
||||||
|
SFR(SPDAT, 0xCF);
|
||||||
|
|
||||||
|
#define _PSW 0xD0
|
||||||
|
SFR(PSW, _PSW);
|
||||||
|
SBIT(CY, _PSW, 7);
|
||||||
|
SBIT(AC, _PSW, 6);
|
||||||
|
SBIT(F0, _PSW, 5);
|
||||||
|
SBIT(RS1, _PSW, 4);
|
||||||
|
SBIT(RS0, _PSW, 3);
|
||||||
|
SBIT(OV, _PSW, 2);
|
||||||
|
SBIT(F1, _PSW, 1);
|
||||||
|
SBIT(P, _PSW, 0);
|
||||||
|
SFR(T4T3M, 0xD1);
|
||||||
|
SFR(T4H, 0xD2);
|
||||||
|
SFR(T4L, 0xD3);
|
||||||
|
SFR(T3H, 0xD4);
|
||||||
|
SFR(T3L, 0xD5);
|
||||||
|
SFR(T2H, 0xD6);
|
||||||
|
SFR(T2L, 0xD7);
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
928
include/fw_reg_stc8g.h
Normal file
928
include/fw_reg_stc8g.h
Normal file
@ -0,0 +1,928 @@
|
|||||||
|
#ifndef __IO_REG_STC8G_H__
|
||||||
|
#define __IO_REG_STC8G_H__
|
||||||
|
|
||||||
|
#include "fw_reg_base.h"
|
||||||
|
|
||||||
|
#define _CCON 0xD8
|
||||||
|
SFR(CCON, _CCON);
|
||||||
|
SBIT(CF, _CCON, 7);
|
||||||
|
SBIT(CR, _CCON, 6);
|
||||||
|
SBIT(CCF2, _CCON, 2);
|
||||||
|
SBIT(CCF1, _CCON, 1);
|
||||||
|
SBIT(CCF0, _CCON, 0);
|
||||||
|
SFR(CMOD, 0xD9);
|
||||||
|
SFR(CCAPM0, 0xDA);
|
||||||
|
SFR(CCAPM1, 0xDB);
|
||||||
|
SFR(CCAPM2, 0xDC);
|
||||||
|
SFR(ADCCFG, 0xDE);
|
||||||
|
SFR(IP3, 0xDF);
|
||||||
|
SFR(ACC, 0xE0);
|
||||||
|
SFR(P7M1, 0xE1);
|
||||||
|
SFR(P7M0, 0xE2);
|
||||||
|
SFR(DPS, 0xE3);
|
||||||
|
SFR(DPL1, 0xE4);
|
||||||
|
SFR(DPH1, 0xE5);
|
||||||
|
SFR(CMPCR1, 0xE6);
|
||||||
|
SFR(CMPCR2, 0xE7);
|
||||||
|
SFR(P6, 0xE8);
|
||||||
|
SFR(CL, 0xE9);
|
||||||
|
SFR(CCAP0L, 0xEA);
|
||||||
|
SFR(CCAP1L, 0xEB);
|
||||||
|
SFR(CCAP2L, 0xEC);
|
||||||
|
SFR(IP3H, 0xEE);
|
||||||
|
SFR(AUXINTIF, 0xEF);
|
||||||
|
|
||||||
|
SFR(B, 0xF0);
|
||||||
|
SFR(PWMSET, 0xF1);
|
||||||
|
SFR(PCA_PWM0, 0xF2);
|
||||||
|
SFR(PCA_PWM1, 0xF3);
|
||||||
|
SFR(PCA_PWM2, 0xF4);
|
||||||
|
SFR(IAP_TPS, 0xF5);
|
||||||
|
SFR(PWMCFG01, 0xF6);
|
||||||
|
SFR(PWMCFG23, 0xF7);
|
||||||
|
SFR(P7, 0xF8);
|
||||||
|
SFR(CH, 0xF9);
|
||||||
|
SFR(CCAP0H, 0xFA);
|
||||||
|
SFR(CCAP1H, 0xFB);
|
||||||
|
SFR(CCAP2H, 0xFC);
|
||||||
|
SFR(PWMCFG45, 0xFE);
|
||||||
|
SFR(RSTCFG, 0xFF);
|
||||||
|
|
||||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FF00H-FFFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define PWM0C (*(unsigned int volatile __XDATA *)0xff00)
|
||||||
|
#define PWM0CH (*(unsigned char volatile __XDATA *)0xff00)
|
||||||
|
#define PWM0CL (*(unsigned char volatile __XDATA *)0xff01)
|
||||||
|
#define PWM0CKS (*(unsigned char volatile __XDATA *)0xff02)
|
||||||
|
#define PWM0TADC (*(unsigned int volatile __XDATA *)0xff03)
|
||||||
|
#define PWM0TADCH (*(unsigned char volatile __XDATA *)0xff03)
|
||||||
|
#define PWM0TADCL (*(unsigned char volatile __XDATA *)0xff04)
|
||||||
|
#define PWM0IF (*(unsigned char volatile __XDATA *)0xff05)
|
||||||
|
#define PWM0FDCR (*(unsigned char volatile __XDATA *)0xff06)
|
||||||
|
#define PWM00T1 (*(unsigned int volatile __XDATA *)0xff10)
|
||||||
|
#define PWM00T1L (*(unsigned char volatile __XDATA *)0xff11)
|
||||||
|
#define PWM00T2 (*(unsigned int volatile __XDATA *)0xff12)
|
||||||
|
#define PWM00T2H (*(unsigned char volatile __XDATA *)0xff12)
|
||||||
|
#define PWM00T2L (*(unsigned char volatile __XDATA *)0xff13)
|
||||||
|
#define PWM00CR (*(unsigned char volatile __XDATA *)0xff14)
|
||||||
|
#define PWM00HLD (*(unsigned char volatile __XDATA *)0xff15)
|
||||||
|
#define PWM01T1 (*(unsigned int volatile __XDATA *)0xff18)
|
||||||
|
#define PWM01T1H (*(unsigned char volatile __XDATA *)0xff18)
|
||||||
|
#define PWM01T1L (*(unsigned char volatile __XDATA *)0xff19)
|
||||||
|
#define PWM01T2 (*(unsigned int volatile __XDATA *)0xff1a)
|
||||||
|
#define PWM01T2H (*(unsigned char volatile __XDATA *)0xff1a)
|
||||||
|
#define PWM01T2L (*(unsigned char volatile __XDATA *)0xff1b)
|
||||||
|
#define PWM01CR (*(unsigned char volatile __XDATA *)0xff1c)
|
||||||
|
#define PWM01HLD (*(unsigned char volatile __XDATA *)0xff1d)
|
||||||
|
#define PWM02T1 (*(unsigned int volatile __XDATA *)0xff20)
|
||||||
|
#define PWM02T1H (*(unsigned char volatile __XDATA *)0xff20)
|
||||||
|
#define PWM02T1L (*(unsigned char volatile __XDATA *)0xff21)
|
||||||
|
#define PWM02T2 (*(unsigned int volatile __XDATA *)0xff22)
|
||||||
|
#define PWM02T2H (*(unsigned char volatile __XDATA *)0xff22)
|
||||||
|
#define PWM02T2L (*(unsigned char volatile __XDATA *)0xff23)
|
||||||
|
#define PWM02CR (*(unsigned char volatile __XDATA *)0xff24)
|
||||||
|
#define PWM02HLD (*(unsigned char volatile __XDATA *)0xff25)
|
||||||
|
#define PWM03T1 (*(unsigned int volatile __XDATA *)0xff28)
|
||||||
|
#define PWM03T1H (*(unsigned char volatile __XDATA *)0xff28)
|
||||||
|
#define PWM03T1L (*(unsigned char volatile __XDATA *)0xff29)
|
||||||
|
#define PWM03T2 (*(unsigned int volatile __XDATA *)0xff2a)
|
||||||
|
#define PWM03T2H (*(unsigned char volatile __XDATA *)0xff2a)
|
||||||
|
#define PWM03T2L (*(unsigned char volatile __XDATA *)0xff2b)
|
||||||
|
#define PWM03CR (*(unsigned char volatile __XDATA *)0xff2c)
|
||||||
|
#define PWM03HLD (*(unsigned char volatile __XDATA *)0xff2d)
|
||||||
|
#define PWM04T1 (*(unsigned int volatile __XDATA *)0xff30)
|
||||||
|
#define PWM04T1H (*(unsigned char volatile __XDATA *)0xff30)
|
||||||
|
#define PWM04T1L (*(unsigned char volatile __XDATA *)0xff31)
|
||||||
|
#define PWM04T2 (*(unsigned int volatile __XDATA *)0xff32)
|
||||||
|
#define PWM04T2H (*(unsigned char volatile __XDATA *)0xff32)
|
||||||
|
#define PWM04T2L (*(unsigned char volatile __XDATA *)0xff33)
|
||||||
|
#define PWM04CR (*(unsigned char volatile __XDATA *)0xff34)
|
||||||
|
#define PWM04HLD (*(unsigned char volatile __XDATA *)0xff35)
|
||||||
|
#define PWM05T1 (*(unsigned int volatile __XDATA *)0xff38)
|
||||||
|
#define PWM05T1H (*(unsigned char volatile __XDATA *)0xff38)
|
||||||
|
#define PWM05T1L (*(unsigned char volatile __XDATA *)0xff39)
|
||||||
|
#define PWM05T2 (*(unsigned int volatile __XDATA *)0xff3a)
|
||||||
|
#define PWM05T2H (*(unsigned char volatile __XDATA *)0xff3a)
|
||||||
|
#define PWM05T2L (*(unsigned char volatile __XDATA *)0xff3b)
|
||||||
|
#define PWM05CR (*(unsigned char volatile __XDATA *)0xff3c)
|
||||||
|
#define PWM05HLD (*(unsigned char volatile __XDATA *)0xff3d)
|
||||||
|
#define PWM06T1 (*(unsigned int volatile __XDATA *)0xff40)
|
||||||
|
#define PWM06T1H (*(unsigned char volatile __XDATA *)0xff40)
|
||||||
|
#define PWM06T1L (*(unsigned char volatile __XDATA *)0xff41)
|
||||||
|
#define PWM06T2 (*(unsigned int volatile __XDATA *)0xff42)
|
||||||
|
#define PWM06T2H (*(unsigned char volatile __XDATA *)0xff42)
|
||||||
|
#define PWM06T2L (*(unsigned char volatile __XDATA *)0xff43)
|
||||||
|
#define PWM06CR (*(unsigned char volatile __XDATA *)0xff44)
|
||||||
|
#define PWM06HLD (*(unsigned char volatile __XDATA *)0xff45)
|
||||||
|
#define PWM07T1 (*(unsigned int volatile __XDATA *)0xff48)
|
||||||
|
#define PWM07T1H (*(unsigned char volatile __XDATA *)0xff48)
|
||||||
|
#define PWM07T1L (*(unsigned char volatile __XDATA *)0xff49)
|
||||||
|
#define PWM07T2 (*(unsigned int volatile __XDATA *)0xff4a)
|
||||||
|
#define PWM07T2H (*(unsigned char volatile __XDATA *)0xff4a)
|
||||||
|
#define PWM07T2L (*(unsigned char volatile __XDATA *)0xff4b)
|
||||||
|
#define PWM07CR (*(unsigned char volatile __XDATA *)0xff4c)
|
||||||
|
#define PWM07HLD (*(unsigned char volatile __XDATA *)0xff4d)
|
||||||
|
#define PWM1C (*(unsigned int volatile __XDATA *)0xff50)
|
||||||
|
#define PWM1CH (*(unsigned char volatile __XDATA *)0xff50)
|
||||||
|
#define PWM1CL (*(unsigned char volatile __XDATA *)0xff51)
|
||||||
|
#define PWM1CKS (*(unsigned char volatile __XDATA *)0xff52)
|
||||||
|
#define PWM1IF (*(unsigned char volatile __XDATA *)0xff55)
|
||||||
|
#define PWM1FDCR (*(unsigned char volatile __XDATA *)0xff56)
|
||||||
|
#define PWM10T1 (*(unsigned int volatile __XDATA *)0xff60)
|
||||||
|
#define PWM10T1H (*(unsigned char volatile __XDATA *)0xff60)
|
||||||
|
#define PWM10T1L (*(unsigned char volatile __XDATA *)0xff61)
|
||||||
|
#define PWM10T2 (*(unsigned int volatile __XDATA *)0xff62)
|
||||||
|
#define PWM10T2H (*(unsigned char volatile __XDATA *)0xff62)
|
||||||
|
#define PWM10T2L (*(unsigned char volatile __XDATA *)0xff63)
|
||||||
|
#define PWM10CR (*(unsigned char volatile __XDATA *)0xff64)
|
||||||
|
#define PWM10HLD (*(unsigned char volatile __XDATA *)0xff65)
|
||||||
|
#define PWM11T1 (*(unsigned int volatile __XDATA *)0xff68)
|
||||||
|
#define PWM11T1H (*(unsigned char volatile __XDATA *)0xff68)
|
||||||
|
#define PWM11T1L (*(unsigned char volatile __XDATA *)0xff69)
|
||||||
|
#define PWM11T2 (*(unsigned int volatile __XDATA *)0xff6a)
|
||||||
|
#define PWM11T2H (*(unsigned char volatile __XDATA *)0xff6a)
|
||||||
|
#define PWM11T2L (*(unsigned char volatile __XDATA *)0xff6b)
|
||||||
|
#define PWM11CR (*(unsigned char volatile __XDATA *)0xff6c)
|
||||||
|
#define PWM11HLD (*(unsigned char volatile __XDATA *)0xff6d)
|
||||||
|
#define PWM12T1 (*(unsigned int volatile __XDATA *)0xff70)
|
||||||
|
#define PWM12T1H (*(unsigned char volatile __XDATA *)0xff70)
|
||||||
|
#define PWM12T1L (*(unsigned char volatile __XDATA *)0xff71)
|
||||||
|
#define PWM12T2 (*(unsigned int volatile __XDATA *)0xff72)
|
||||||
|
#define PWM12T2H (*(unsigned char volatile __XDATA *)0xff72)
|
||||||
|
#define PWM12T2L (*(unsigned char volatile __XDATA *)0xff73)
|
||||||
|
#define PWM12CR (*(unsigned char volatile __XDATA *)0xff74)
|
||||||
|
#define PWM12HLD (*(unsigned char volatile __XDATA *)0xff75)
|
||||||
|
#define PWM13T1 (*(unsigned int volatile __XDATA *)0xff78)
|
||||||
|
#define PWM13T1H (*(unsigned char volatile __XDATA *)0xff78)
|
||||||
|
#define PWM13T1L (*(unsigned char volatile __XDATA *)0xff79)
|
||||||
|
#define PWM13T2 (*(unsigned int volatile __XDATA *)0xff7a)
|
||||||
|
#define PWM13T2H (*(unsigned char volatile __XDATA *)0xff7a)
|
||||||
|
#define PWM13T2L (*(unsigned char volatile __XDATA *)0xff7b)
|
||||||
|
#define PWM13CR (*(unsigned char volatile __XDATA *)0xff7c)
|
||||||
|
#define PWM13HLD (*(unsigned char volatile __XDATA *)0xff7d)
|
||||||
|
#define PWM14T1 (*(unsigned int volatile __XDATA *)0xff80)
|
||||||
|
#define PWM14T1H (*(unsigned char volatile __XDATA *)0xff80)
|
||||||
|
#define PWM14T1L (*(unsigned char volatile __XDATA *)0xff81)
|
||||||
|
#define PWM14T2 (*(unsigned int volatile __XDATA *)0xff82)
|
||||||
|
#define PWM14T2H (*(unsigned char volatile __XDATA *)0xff82)
|
||||||
|
#define PWM14T2L (*(unsigned char volatile __XDATA *)0xff83)
|
||||||
|
#define PWM14CR (*(unsigned char volatile __XDATA *)0xff84)
|
||||||
|
#define PWM14HLD (*(unsigned char volatile __XDATA *)0xff85)
|
||||||
|
#define PWM15T1 (*(unsigned int volatile __XDATA *)0xff88)
|
||||||
|
#define PWM15T1H (*(unsigned char volatile __XDATA *)0xff88)
|
||||||
|
#define PWM15T1L (*(unsigned char volatile __XDATA *)0xff89)
|
||||||
|
#define PWM15T2 (*(unsigned int volatile __XDATA *)0xff8a)
|
||||||
|
#define PWM15T2H (*(unsigned char volatile __XDATA *)0xff8a)
|
||||||
|
#define PWM15T2L (*(unsigned char volatile __XDATA *)0xff8b)
|
||||||
|
#define PWM15CR (*(unsigned char volatile __XDATA *)0xff8c)
|
||||||
|
#define PWM15HLD (*(unsigned char volatile __XDATA *)0xff8d)
|
||||||
|
#define PWM16T1 (*(unsigned int volatile __XDATA *)0xff90)
|
||||||
|
#define PWM16T1H (*(unsigned char volatile __XDATA *)0xff90)
|
||||||
|
#define PWM16T1L (*(unsigned char volatile __XDATA *)0xff91)
|
||||||
|
#define PWM16T2 (*(unsigned int volatile __XDATA *)0xff92)
|
||||||
|
#define PWM16T2H (*(unsigned char volatile __XDATA *)0xff92)
|
||||||
|
#define PWM16T2L (*(unsigned char volatile __XDATA *)0xff93)
|
||||||
|
#define PWM16CR (*(unsigned char volatile __XDATA *)0xff94)
|
||||||
|
#define PWM16HLD (*(unsigned char volatile __XDATA *)0xff95)
|
||||||
|
#define PWM17T1 (*(unsigned int volatile __XDATA *)0xff98)
|
||||||
|
#define PWM17T1H (*(unsigned char volatile __XDATA *)0xff98)
|
||||||
|
#define PWM17T1L (*(unsigned char volatile __XDATA *)0xff99)
|
||||||
|
#define PWM17T2 (*(unsigned int volatile __XDATA *)0xff9a)
|
||||||
|
#define PWM17T2H (*(unsigned char volatile __XDATA *)0xff9a)
|
||||||
|
#define PWM17T2L (*(unsigned char volatile __XDATA *)0xff9b)
|
||||||
|
#define PWM17CR (*(unsigned char volatile __XDATA *)0xff9c)
|
||||||
|
#define PWM17HLD (*(unsigned char volatile __XDATA *)0xff9d)
|
||||||
|
#define PWM2C (*(unsigned int volatile __XDATA *)0xffa0)
|
||||||
|
#define PWM2CH (*(unsigned char volatile __XDATA *)0xffa0)
|
||||||
|
#define PWM2CL (*(unsigned char volatile __XDATA *)0xffa1)
|
||||||
|
#define PWM2CKS (*(unsigned char volatile __XDATA *)0xffa2)
|
||||||
|
#define PWM2TADC (*(unsigned int volatile __XDATA *)0xffa3)
|
||||||
|
#define PWM2TADCH (*(unsigned char volatile __XDATA *)0xffa3)
|
||||||
|
#define PWM2TADCL (*(unsigned char volatile __XDATA *)0xffa4)
|
||||||
|
#define PWM2IF (*(unsigned char volatile __XDATA *)0xffa5)
|
||||||
|
#define PWM2FDCR (*(unsigned char volatile __XDATA *)0xffa6)
|
||||||
|
#define PWM20T1 (*(unsigned int volatile __XDATA *)0xffb0)
|
||||||
|
#define PWM20T1H (*(unsigned char volatile __XDATA *)0xffb0)
|
||||||
|
#define PWM20T1L (*(unsigned char volatile __XDATA *)0xffb1)
|
||||||
|
#define PWM20T2 (*(unsigned int volatile __XDATA *)0xffb2)
|
||||||
|
#define PWM20T2H (*(unsigned char volatile __XDATA *)0xffb2)
|
||||||
|
#define PWM20T2L (*(unsigned char volatile __XDATA *)0xffb3)
|
||||||
|
#define PWM20CR (*(unsigned char volatile __XDATA *)0xffb4)
|
||||||
|
#define PWM20HLD (*(unsigned char volatile __XDATA *)0xffb5)
|
||||||
|
#define PWM21T1 (*(unsigned int volatile __XDATA *)0xffb8)
|
||||||
|
#define PWM21T1H (*(unsigned char volatile __XDATA *)0xffb8)
|
||||||
|
#define PWM21T1L (*(unsigned char volatile __XDATA *)0xffb9)
|
||||||
|
#define PWM21T2 (*(unsigned int volatile __XDATA *)0xffba)
|
||||||
|
#define PWM21T2H (*(unsigned char volatile __XDATA *)0xffba)
|
||||||
|
#define PWM21T2L (*(unsigned char volatile __XDATA *)0xffbb)
|
||||||
|
#define PWM21CR (*(unsigned char volatile __XDATA *)0xffbc)
|
||||||
|
#define PWM21HLD (*(unsigned char volatile __XDATA *)0xffbd)
|
||||||
|
#define PWM22T1 (*(unsigned int volatile __XDATA *)0xffc0)
|
||||||
|
#define PWM22T1H (*(unsigned char volatile __XDATA *)0xffc0)
|
||||||
|
#define PWM22T1L (*(unsigned char volatile __XDATA *)0xffc1)
|
||||||
|
#define PWM22T2 (*(unsigned int volatile __XDATA *)0xffc2)
|
||||||
|
#define PWM22T2H (*(unsigned char volatile __XDATA *)0xffc2)
|
||||||
|
#define PWM22T2L (*(unsigned char volatile __XDATA *)0xffc3)
|
||||||
|
#define PWM22CR (*(unsigned char volatile __XDATA *)0xffc4)
|
||||||
|
#define PWM22HLD (*(unsigned char volatile __XDATA *)0xffc5)
|
||||||
|
#define PWM23T1 (*(unsigned int volatile __XDATA *)0xffc8)
|
||||||
|
#define PWM23T1H (*(unsigned char volatile __XDATA *)0xffc8)
|
||||||
|
#define PWM23T1L (*(unsigned char volatile __XDATA *)0xffc9)
|
||||||
|
#define PWM23T2 (*(unsigned int volatile __XDATA *)0xffca)
|
||||||
|
#define PWM23T2H (*(unsigned char volatile __XDATA *)0xffca)
|
||||||
|
#define PWM23T2L (*(unsigned char volatile __XDATA *)0xffcb)
|
||||||
|
#define PWM23CR (*(unsigned char volatile __XDATA *)0xffcc)
|
||||||
|
#define PWM23HLD (*(unsigned char volatile __XDATA *)0xffcd)
|
||||||
|
#define PWM24T1 (*(unsigned int volatile __XDATA *)0xffd0)
|
||||||
|
#define PWM24T1H (*(unsigned char volatile __XDATA *)0xffd0)
|
||||||
|
#define PWM24T1L (*(unsigned char volatile __XDATA *)0xffd1)
|
||||||
|
#define PWM24T2 (*(unsigned int volatile __XDATA *)0xffd2)
|
||||||
|
#define PWM24T2H (*(unsigned char volatile __XDATA *)0xffd2)
|
||||||
|
#define PWM24T2L (*(unsigned char volatile __XDATA *)0xffd3)
|
||||||
|
#define PWM24CR (*(unsigned char volatile __XDATA *)0xffd4)
|
||||||
|
#define PWM24HLD (*(unsigned char volatile __XDATA *)0xffd5)
|
||||||
|
#define PWM25T1 (*(unsigned int volatile __XDATA *)0xffd8)
|
||||||
|
#define PWM25T1H (*(unsigned char volatile __XDATA *)0xffd8)
|
||||||
|
#define PWM25T1L (*(unsigned char volatile __XDATA *)0xffd9)
|
||||||
|
#define PWM25T2 (*(unsigned int volatile __XDATA *)0xffda)
|
||||||
|
#define PWM25T2H (*(unsigned char volatile __XDATA *)0xffda)
|
||||||
|
#define PWM25T2L (*(unsigned char volatile __XDATA *)0xffdb)
|
||||||
|
#define PWM25CR (*(unsigned char volatile __XDATA *)0xffdc)
|
||||||
|
#define PWM25HLD (*(unsigned char volatile __XDATA *)0xffdd)
|
||||||
|
#define PWM26T1 (*(unsigned int volatile __XDATA *)0xffe0)
|
||||||
|
#define PWM26T1H (*(unsigned char volatile __XDATA *)0xffe0)
|
||||||
|
#define PWM26T1L (*(unsigned char volatile __XDATA *)0xffe1)
|
||||||
|
#define PWM26T2 (*(unsigned int volatile __XDATA *)0xffe2)
|
||||||
|
#define PWM26T2H (*(unsigned char volatile __XDATA *)0xffe2)
|
||||||
|
#define PWM26T2L (*(unsigned char volatile __XDATA *)0xffe3)
|
||||||
|
#define PWM26CR (*(unsigned char volatile __XDATA *)0xffe4)
|
||||||
|
#define PWM26HLD (*(unsigned char volatile __XDATA *)0xffe5)
|
||||||
|
#define PWM27T1 (*(unsigned int volatile __XDATA *)0xffe8)
|
||||||
|
#define PWM27T1H (*(unsigned char volatile __XDATA *)0xffe8)
|
||||||
|
#define PWM27T1L (*(unsigned char volatile __XDATA *)0xffe9)
|
||||||
|
#define PWM27T2 (*(unsigned int volatile __XDATA *)0xffea)
|
||||||
|
#define PWM27T2H (*(unsigned char volatile __XDATA *)0xffea)
|
||||||
|
#define PWM27T2L (*(unsigned char volatile __XDATA *)0xffeb)
|
||||||
|
#define PWM27CR (*(unsigned char volatile __XDATA *)0xffec)
|
||||||
|
#define PWM27HLD (*(unsigned char volatile __XDATA *)0xffed)
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FE00H-FEFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define CKSEL (*(unsigned char volatile __XDATA *)0xfe00)
|
||||||
|
#define CLKDIV (*(unsigned char volatile __XDATA *)0xfe01)
|
||||||
|
#define HIRCCR (*(unsigned char volatile __XDATA *)0xfe02)
|
||||||
|
#define XOSCCR (*(unsigned char volatile __XDATA *)0xfe03)
|
||||||
|
#define IRC32KCR (*(unsigned char volatile __XDATA *)0xfe04)
|
||||||
|
#define MCLKOCR (*(unsigned char volatile __XDATA *)0xfe05)
|
||||||
|
#define IRCDB (*(unsigned char volatile __XDATA *)0xfe06)
|
||||||
|
#define X32KCR (*(unsigned char volatile __XDATA *)0xfe08)
|
||||||
|
|
||||||
|
#define P0PU (*(unsigned char volatile __XDATA *)0xfe10)
|
||||||
|
#define P1PU (*(unsigned char volatile __XDATA *)0xfe11)
|
||||||
|
#define P2PU (*(unsigned char volatile __XDATA *)0xfe12)
|
||||||
|
#define P3PU (*(unsigned char volatile __XDATA *)0xfe13)
|
||||||
|
#define P4PU (*(unsigned char volatile __XDATA *)0xfe14)
|
||||||
|
#define P5PU (*(unsigned char volatile __XDATA *)0xfe15)
|
||||||
|
#define P6PU (*(unsigned char volatile __XDATA *)0xfe16)
|
||||||
|
#define P7PU (*(unsigned char volatile __XDATA *)0xfe17)
|
||||||
|
#define P0NCS (*(unsigned char volatile __XDATA *)0xfe18)
|
||||||
|
#define P1NCS (*(unsigned char volatile __XDATA *)0xfe19)
|
||||||
|
#define P2NCS (*(unsigned char volatile __XDATA *)0xfe1a)
|
||||||
|
#define P3NCS (*(unsigned char volatile __XDATA *)0xfe1b)
|
||||||
|
#define P4NCS (*(unsigned char volatile __XDATA *)0xfe1c)
|
||||||
|
#define P5NCS (*(unsigned char volatile __XDATA *)0xfe1d)
|
||||||
|
#define P6NCS (*(unsigned char volatile __XDATA *)0xfe1e)
|
||||||
|
#define P7NCS (*(unsigned char volatile __XDATA *)0xfe1f)
|
||||||
|
#define P0SR (*(unsigned char volatile __XDATA *)0xfe20)
|
||||||
|
#define P1SR (*(unsigned char volatile __XDATA *)0xfe21)
|
||||||
|
#define P2SR (*(unsigned char volatile __XDATA *)0xfe22)
|
||||||
|
#define P3SR (*(unsigned char volatile __XDATA *)0xfe23)
|
||||||
|
#define P4SR (*(unsigned char volatile __XDATA *)0xfe24)
|
||||||
|
#define P5SR (*(unsigned char volatile __XDATA *)0xfe25)
|
||||||
|
#define P6SR (*(unsigned char volatile __XDATA *)0xfe26)
|
||||||
|
#define P7SR (*(unsigned char volatile __XDATA *)0xfe27)
|
||||||
|
#define P0DR (*(unsigned char volatile __XDATA *)0xfe28)
|
||||||
|
#define P1DR (*(unsigned char volatile __XDATA *)0xfe29)
|
||||||
|
#define P2DR (*(unsigned char volatile __XDATA *)0xfe2a)
|
||||||
|
#define P3DR (*(unsigned char volatile __XDATA *)0xfe2b)
|
||||||
|
#define P4DR (*(unsigned char volatile __XDATA *)0xfe2c)
|
||||||
|
#define P5DR (*(unsigned char volatile __XDATA *)0xfe2d)
|
||||||
|
#define P6DR (*(unsigned char volatile __XDATA *)0xfe2e)
|
||||||
|
#define P7DR (*(unsigned char volatile __XDATA *)0xfe2f)
|
||||||
|
#define P0IE (*(unsigned char volatile __XDATA *)0xfe30)
|
||||||
|
#define P1IE (*(unsigned char volatile __XDATA *)0xfe31)
|
||||||
|
#define P2IE (*(unsigned char volatile __XDATA *)0xfe32)
|
||||||
|
#define P3IE (*(unsigned char volatile __XDATA *)0xfe33)
|
||||||
|
#define P4IE (*(unsigned char volatile __XDATA *)0xfe34)
|
||||||
|
#define P5IE (*(unsigned char volatile __XDATA *)0xfe35)
|
||||||
|
#define P6IE (*(unsigned char volatile __XDATA *)0xfe36)
|
||||||
|
#define P7IE (*(unsigned char volatile __XDATA *)0xfe37)
|
||||||
|
|
||||||
|
#define RTCCR (*(unsigned char volatile __XDATA *)0xfe60)
|
||||||
|
#define RTCCFG (*(unsigned char volatile __XDATA *)0xfe61)
|
||||||
|
#define RTCIEN (*(unsigned char volatile __XDATA *)0xfe62)
|
||||||
|
#define RTCIF (*(unsigned char volatile __XDATA *)0xfe63)
|
||||||
|
#define ALAHOUR (*(unsigned char volatile __XDATA *)0xfe64)
|
||||||
|
#define ALAMIN (*(unsigned char volatile __XDATA *)0xfe65)
|
||||||
|
#define ALASEC (*(unsigned char volatile __XDATA *)0xfe66)
|
||||||
|
#define ALASSEC (*(unsigned char volatile __XDATA *)0xfe67)
|
||||||
|
#define INIYEAR (*(unsigned char volatile __XDATA *)0xfe68)
|
||||||
|
#define INIMONTH (*(unsigned char volatile __XDATA *)0xfe69)
|
||||||
|
#define INIDAY (*(unsigned char volatile __XDATA *)0xfe6a)
|
||||||
|
#define INIHOUR (*(unsigned char volatile __XDATA *)0xfe6b)
|
||||||
|
#define INIMIN (*(unsigned char volatile __XDATA *)0xfe6c)
|
||||||
|
#define INISEC (*(unsigned char volatile __XDATA *)0xfe6d)
|
||||||
|
#define INISSEC (*(unsigned char volatile __XDATA *)0xfe6e)
|
||||||
|
#define YEAR (*(unsigned char volatile __XDATA *)0xfe70)
|
||||||
|
#define MONTH (*(unsigned char volatile __XDATA *)0xfe71)
|
||||||
|
#define DAY (*(unsigned char volatile __XDATA *)0xfe72)
|
||||||
|
#define HOUR (*(unsigned char volatile __XDATA *)0xfe73)
|
||||||
|
#define MIN (*(unsigned char volatile __XDATA *)0xfe74)
|
||||||
|
#define SEC (*(unsigned char volatile __XDATA *)0xfe75)
|
||||||
|
#define SSEC (*(unsigned char volatile __XDATA *)0xfe76)
|
||||||
|
|
||||||
|
#define I2CCFG (*(unsigned char volatile __XDATA *)0xfe80)
|
||||||
|
#define I2CMSCR (*(unsigned char volatile __XDATA *)0xfe81)
|
||||||
|
#define I2CMSST (*(unsigned char volatile __XDATA *)0xfe82)
|
||||||
|
#define I2CSLCR (*(unsigned char volatile __XDATA *)0xfe83)
|
||||||
|
#define I2CSLST (*(unsigned char volatile __XDATA *)0xfe84)
|
||||||
|
#define I2CSLADR (*(unsigned char volatile __XDATA *)0xfe85)
|
||||||
|
#define I2CTXD (*(unsigned char volatile __XDATA *)0xfe86)
|
||||||
|
#define I2CRXD (*(unsigned char volatile __XDATA *)0xfe87)
|
||||||
|
#define I2CMSAUX (*(unsigned char volatile __XDATA *)0xfe88)
|
||||||
|
|
||||||
|
#define TM2PS (*(unsigned char volatile __XDATA *)0xfea2)
|
||||||
|
#define TM3PS (*(unsigned char volatile __XDATA *)0xfea3)
|
||||||
|
#define TM4PS (*(unsigned char volatile __XDATA *)0xfea4)
|
||||||
|
#define ADCTIM (*(unsigned char volatile __XDATA *)0xfea8)
|
||||||
|
#define T3T4PS (*(unsigned char volatile __XDATA *)0xfeac)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FD00H-FDFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define PxINTE 0xfd00
|
||||||
|
#define P0INTE (*(unsigned char volatile __XDATA *)0xfd00)
|
||||||
|
#define P1INTE (*(unsigned char volatile __XDATA *)0xfd01)
|
||||||
|
#define P2INTE (*(unsigned char volatile __XDATA *)0xfd02)
|
||||||
|
#define P3INTE (*(unsigned char volatile __XDATA *)0xfd03)
|
||||||
|
#define P4INTE (*(unsigned char volatile __XDATA *)0xfd04)
|
||||||
|
#define P5INTE (*(unsigned char volatile __XDATA *)0xfd05)
|
||||||
|
#define P6INTE (*(unsigned char volatile __XDATA *)0xfd06)
|
||||||
|
#define P7INTE (*(unsigned char volatile __XDATA *)0xfd07)
|
||||||
|
#define P0INTF (*(unsigned char volatile __XDATA *)0xfd10)
|
||||||
|
#define P1INTF (*(unsigned char volatile __XDATA *)0xfd11)
|
||||||
|
#define P2INTF (*(unsigned char volatile __XDATA *)0xfd12)
|
||||||
|
#define P3INTF (*(unsigned char volatile __XDATA *)0xfd13)
|
||||||
|
#define P4INTF (*(unsigned char volatile __XDATA *)0xfd14)
|
||||||
|
#define P5INTF (*(unsigned char volatile __XDATA *)0xfd15)
|
||||||
|
#define P6INTF (*(unsigned char volatile __XDATA *)0xfd16)
|
||||||
|
#define P7INTF (*(unsigned char volatile __XDATA *)0xfd17)
|
||||||
|
#define PxIM0 0xfd20
|
||||||
|
#define P0IM0 (*(unsigned char volatile __XDATA *)0xfd20)
|
||||||
|
#define P1IM0 (*(unsigned char volatile __XDATA *)0xfd21)
|
||||||
|
#define P2IM0 (*(unsigned char volatile __XDATA *)0xfd22)
|
||||||
|
#define P3IM0 (*(unsigned char volatile __XDATA *)0xfd23)
|
||||||
|
#define P4IM0 (*(unsigned char volatile __XDATA *)0xfd24)
|
||||||
|
#define P5IM0 (*(unsigned char volatile __XDATA *)0xfd25)
|
||||||
|
#define P6IM0 (*(unsigned char volatile __XDATA *)0xfd26)
|
||||||
|
#define P7IM0 (*(unsigned char volatile __XDATA *)0xfd27)
|
||||||
|
#define PxIM1 0xfd30
|
||||||
|
#define P0IM1 (*(unsigned char volatile __XDATA *)0xfd30)
|
||||||
|
#define P1IM1 (*(unsigned char volatile __XDATA *)0xfd31)
|
||||||
|
#define P2IM1 (*(unsigned char volatile __XDATA *)0xfd32)
|
||||||
|
#define P3IM1 (*(unsigned char volatile __XDATA *)0xfd33)
|
||||||
|
#define P4IM1 (*(unsigned char volatile __XDATA *)0xfd34)
|
||||||
|
#define P5IM1 (*(unsigned char volatile __XDATA *)0xfd35)
|
||||||
|
#define P6IM1 (*(unsigned char volatile __XDATA *)0xfd36)
|
||||||
|
#define P7IM1 (*(unsigned char volatile __XDATA *)0xfd37)
|
||||||
|
#define P0WKUE (*(unsigned char volatile __XDATA *)0xfd40)
|
||||||
|
#define P1WKUE (*(unsigned char volatile __XDATA *)0xfd41)
|
||||||
|
#define P2WKUE (*(unsigned char volatile __XDATA *)0xfd42)
|
||||||
|
#define P3WKUE (*(unsigned char volatile __XDATA *)0xfd43)
|
||||||
|
#define P4WKUE (*(unsigned char volatile __XDATA *)0xfd44)
|
||||||
|
#define P5WKUE (*(unsigned char volatile __XDATA *)0xfd45)
|
||||||
|
#define P6WKUE (*(unsigned char volatile __XDATA *)0xfd46)
|
||||||
|
#define P7WKUE (*(unsigned char volatile __XDATA *)0xfd47)
|
||||||
|
#define PIN_IP (*(unsigned char volatile __XDATA *)0xfd60)
|
||||||
|
#define PIN_IPH (*(unsigned char volatile __XDATA *)0xfd61)
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FC00H-FCFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define PWM3C (*(unsigned int volatile __XDATA *)0xfc00)
|
||||||
|
#define PWM3CH (*(unsigned char volatile __XDATA *)0xfc00)
|
||||||
|
#define PWM3CL (*(unsigned char volatile __XDATA *)0xfc01)
|
||||||
|
#define PWM3CKS (*(unsigned char volatile __XDATA *)0xfc02)
|
||||||
|
#define PWM3IF (*(unsigned char volatile __XDATA *)0xfc05)
|
||||||
|
#define PWM3FDCR (*(unsigned char volatile __XDATA *)0xfc06)
|
||||||
|
#define PWM30T1 (*(unsigned int volatile __XDATA *)0xfc10)
|
||||||
|
#define PWM30T1H (*(unsigned char volatile __XDATA *)0xfc10)
|
||||||
|
#define PWM30T1L (*(unsigned char volatile __XDATA *)0xfc11)
|
||||||
|
#define PWM30T2 (*(unsigned int volatile __XDATA *)0xfc12)
|
||||||
|
#define PWM30T2H (*(unsigned char volatile __XDATA *)0xfc12)
|
||||||
|
#define PWM30T2L (*(unsigned char volatile __XDATA *)0xfc13)
|
||||||
|
#define PWM30CR (*(unsigned char volatile __XDATA *)0xfc14)
|
||||||
|
#define PWM30HLD (*(unsigned char volatile __XDATA *)0xfc15)
|
||||||
|
#define PWM31T1 (*(unsigned int volatile __XDATA *)0xfc18)
|
||||||
|
#define PWM31T1H (*(unsigned char volatile __XDATA *)0xfc18)
|
||||||
|
#define PWM31T1L (*(unsigned char volatile __XDATA *)0xfc19)
|
||||||
|
#define PWM31T2 (*(unsigned int volatile __XDATA *)0xfc1a)
|
||||||
|
#define PWM31T2H (*(unsigned char volatile __XDATA *)0xfc1a)
|
||||||
|
#define PWM31T2L (*(unsigned char volatile __XDATA *)0xfc1b)
|
||||||
|
#define PWM31CR (*(unsigned char volatile __XDATA *)0xfc1c)
|
||||||
|
#define PWM31HLD (*(unsigned char volatile __XDATA *)0xfc1d)
|
||||||
|
#define PWM32T1 (*(unsigned int volatile __XDATA *)0xfc20)
|
||||||
|
#define PWM32T1H (*(unsigned char volatile __XDATA *)0xfc20)
|
||||||
|
#define PWM32T1L (*(unsigned char volatile __XDATA *)0xfc21)
|
||||||
|
#define PWM32T2 (*(unsigned int volatile __XDATA *)0xfc22)
|
||||||
|
#define PWM32T2H (*(unsigned char volatile __XDATA *)0xfc22)
|
||||||
|
#define PWM32T2L (*(unsigned char volatile __XDATA *)0xfc23)
|
||||||
|
#define PWM32CR (*(unsigned char volatile __XDATA *)0xfc24)
|
||||||
|
#define PWM32HLD (*(unsigned char volatile __XDATA *)0xfc25)
|
||||||
|
#define PWM33T1 (*(unsigned int volatile __XDATA *)0xfc28)
|
||||||
|
#define PWM33T1H (*(unsigned char volatile __XDATA *)0xfc28)
|
||||||
|
#define PWM33T1L (*(unsigned char volatile __XDATA *)0xfc29)
|
||||||
|
#define PWM33T2 (*(unsigned int volatile __XDATA *)0xfc2a)
|
||||||
|
#define PWM33T2H (*(unsigned char volatile __XDATA *)0xfc2a)
|
||||||
|
#define PWM33T2L (*(unsigned char volatile __XDATA *)0xfc2b)
|
||||||
|
#define PWM33CR (*(unsigned char volatile __XDATA *)0xfc2c)
|
||||||
|
#define PWM33HLD (*(unsigned char volatile __XDATA *)0xfc2d)
|
||||||
|
#define PWM34T1 (*(unsigned int volatile __XDATA *)0xfc30)
|
||||||
|
#define PWM34T1H (*(unsigned char volatile __XDATA *)0xfc30)
|
||||||
|
#define PWM34T1L (*(unsigned char volatile __XDATA *)0xfc31)
|
||||||
|
#define PWM34T2 (*(unsigned int volatile __XDATA *)0xfc32)
|
||||||
|
#define PWM34T2H (*(unsigned char volatile __XDATA *)0xfc32)
|
||||||
|
#define PWM34T2L (*(unsigned char volatile __XDATA *)0xfc33)
|
||||||
|
#define PWM34CR (*(unsigned char volatile __XDATA *)0xfc34)
|
||||||
|
#define PWM34HLD (*(unsigned char volatile __XDATA *)0xfc35)
|
||||||
|
#define PWM35T1 (*(unsigned int volatile __XDATA *)0xfc38)
|
||||||
|
#define PWM35T1H (*(unsigned char volatile __XDATA *)0xfc38)
|
||||||
|
#define PWM35T1L (*(unsigned char volatile __XDATA *)0xfc39)
|
||||||
|
#define PWM35T2 (*(unsigned int volatile __XDATA *)0xfc3a)
|
||||||
|
#define PWM35T2H (*(unsigned char volatile __XDATA *)0xfc3a)
|
||||||
|
#define PWM35T2L (*(unsigned char volatile __XDATA *)0xfc3b)
|
||||||
|
#define PWM35CR (*(unsigned char volatile __XDATA *)0xfc3c)
|
||||||
|
#define PWM35HLD (*(unsigned char volatile __XDATA *)0xfc3d)
|
||||||
|
#define PWM36T1 (*(unsigned int volatile __XDATA *)0xfc40)
|
||||||
|
#define PWM36T1H (*(unsigned char volatile __XDATA *)0xfc40)
|
||||||
|
#define PWM36T1L (*(unsigned char volatile __XDATA *)0xfc41)
|
||||||
|
#define PWM36T2 (*(unsigned int volatile __XDATA *)0xfc42)
|
||||||
|
#define PWM36T2H (*(unsigned char volatile __XDATA *)0xfc42)
|
||||||
|
#define PWM36T2L (*(unsigned char volatile __XDATA *)0xfc43)
|
||||||
|
#define PWM36CR (*(unsigned char volatile __XDATA *)0xfc44)
|
||||||
|
#define PWM36HLD (*(unsigned char volatile __XDATA *)0xfc45)
|
||||||
|
#define PWM37T1 (*(unsigned int volatile __XDATA *)0xfc48)
|
||||||
|
#define PWM37T1H (*(unsigned char volatile __XDATA *)0xfc48)
|
||||||
|
#define PWM37T1L (*(unsigned char volatile __XDATA *)0xfc49)
|
||||||
|
#define PWM37T2 (*(unsigned int volatile __XDATA *)0xfc4a)
|
||||||
|
#define PWM37T2H (*(unsigned char volatile __XDATA *)0xfc4a)
|
||||||
|
#define PWM37T2L (*(unsigned char volatile __XDATA *)0xfc4b)
|
||||||
|
#define PWM37CR (*(unsigned char volatile __XDATA *)0xfc4c)
|
||||||
|
#define PWM37HLD (*(unsigned char volatile __XDATA *)0xfc4d)
|
||||||
|
#define PWM4C (*(unsigned int volatile __XDATA *)0xfc50)
|
||||||
|
#define PWM4CH (*(unsigned char volatile __XDATA *)0xfc50)
|
||||||
|
#define PWM4CL (*(unsigned char volatile __XDATA *)0xfc51)
|
||||||
|
#define PWM4CKS (*(unsigned char volatile __XDATA *)0xfc52)
|
||||||
|
#define PWM4TADC (*(unsigned int volatile __XDATA *)0xfc53)
|
||||||
|
#define PWM4TADCH (*(unsigned char volatile __XDATA *)0xfc53)
|
||||||
|
#define PWM4TADCL (*(unsigned char volatile __XDATA *)0xfc54)
|
||||||
|
#define PWM4IF (*(unsigned char volatile __XDATA *)0xfc55)
|
||||||
|
#define PWM4FDCR (*(unsigned char volatile __XDATA *)0xfc56)
|
||||||
|
#define PWM40T1 (*(unsigned int volatile __XDATA *)0xfc60)
|
||||||
|
#define PWM40T1H (*(unsigned char volatile __XDATA *)0xfc60)
|
||||||
|
#define PWM40T1L (*(unsigned char volatile __XDATA *)0xfc61)
|
||||||
|
#define PWM40T2 (*(unsigned int volatile __XDATA *)0xfc62)
|
||||||
|
#define PWM40T2H (*(unsigned char volatile __XDATA *)0xfc62)
|
||||||
|
#define PWM40T2L (*(unsigned char volatile __XDATA *)0xfc63)
|
||||||
|
#define PWM40CR (*(unsigned char volatile __XDATA *)0xfc64)
|
||||||
|
#define PWM40HLD (*(unsigned char volatile __XDATA *)0xfc65)
|
||||||
|
#define PWM41T1 (*(unsigned int volatile __XDATA *)0xfc68)
|
||||||
|
#define PWM41T1H (*(unsigned char volatile __XDATA *)0xfc68)
|
||||||
|
#define PWM41T1L (*(unsigned char volatile __XDATA *)0xfc69)
|
||||||
|
#define PWM41T2 (*(unsigned int volatile __XDATA *)0xfc6a)
|
||||||
|
#define PWM41T2H (*(unsigned char volatile __XDATA *)0xfc6a)
|
||||||
|
#define PWM41T2L (*(unsigned char volatile __XDATA *)0xfc6b)
|
||||||
|
#define PWM41CR (*(unsigned char volatile __XDATA *)0xfc6c)
|
||||||
|
#define PWM41HLD (*(unsigned char volatile __XDATA *)0xfc6d)
|
||||||
|
#define PWM42T1 (*(unsigned int volatile __XDATA *)0xfc70)
|
||||||
|
#define PWM42T1H (*(unsigned char volatile __XDATA *)0xfc70)
|
||||||
|
#define PWM42T1L (*(unsigned char volatile __XDATA *)0xfc71)
|
||||||
|
#define PWM42T2 (*(unsigned int volatile __XDATA *)0xfc72)
|
||||||
|
#define PWM42T2H (*(unsigned char volatile __XDATA *)0xfc72)
|
||||||
|
#define PWM42T2L (*(unsigned char volatile __XDATA *)0xfc73)
|
||||||
|
#define PWM42CR (*(unsigned char volatile __XDATA *)0xfc74)
|
||||||
|
#define PWM42HLD (*(unsigned char volatile __XDATA *)0xfc75)
|
||||||
|
#define PWM43T1 (*(unsigned int volatile __XDATA *)0xfc78)
|
||||||
|
#define PWM43T1H (*(unsigned char volatile __XDATA *)0xfc78)
|
||||||
|
#define PWM43T1L (*(unsigned char volatile __XDATA *)0xfc79)
|
||||||
|
#define PWM43T2 (*(unsigned int volatile __XDATA *)0xfc7a)
|
||||||
|
#define PWM43T2H (*(unsigned char volatile __XDATA *)0xfc7a)
|
||||||
|
#define PWM43T2L (*(unsigned char volatile __XDATA *)0xfc7b)
|
||||||
|
#define PWM43CR (*(unsigned char volatile __XDATA *)0xfc7c)
|
||||||
|
#define PWM43HLD (*(unsigned char volatile __XDATA *)0xfc7d)
|
||||||
|
#define PWM44T1 (*(unsigned int volatile __XDATA *)0xfc80)
|
||||||
|
#define PWM44T1H (*(unsigned char volatile __XDATA *)0xfc80)
|
||||||
|
#define PWM44T1L (*(unsigned char volatile __XDATA *)0xfc81)
|
||||||
|
#define PWM44T2 (*(unsigned int volatile __XDATA *)0xfc82)
|
||||||
|
#define PWM44T2H (*(unsigned char volatile __XDATA *)0xfc82)
|
||||||
|
#define PWM44T2L (*(unsigned char volatile __XDATA *)0xfc83)
|
||||||
|
#define PWM44CR (*(unsigned char volatile __XDATA *)0xfc84)
|
||||||
|
#define PWM44HLD (*(unsigned char volatile __XDATA *)0xfc85)
|
||||||
|
#define PWM45T1 (*(unsigned int volatile __XDATA *)0xfc88)
|
||||||
|
#define PWM45T1H (*(unsigned char volatile __XDATA *)0xfc88)
|
||||||
|
#define PWM45T1L (*(unsigned char volatile __XDATA *)0xfc89)
|
||||||
|
#define PWM45T2 (*(unsigned int volatile __XDATA *)0xfc8a)
|
||||||
|
#define PWM45T2H (*(unsigned char volatile __XDATA *)0xfc8a)
|
||||||
|
#define PWM45T2L (*(unsigned char volatile __XDATA *)0xfc8b)
|
||||||
|
#define PWM45CR (*(unsigned char volatile __XDATA *)0xfc8c)
|
||||||
|
#define PWM45HLD (*(unsigned char volatile __XDATA *)0xfc8d)
|
||||||
|
#define PWM46T1 (*(unsigned int volatile __XDATA *)0xfc90)
|
||||||
|
#define PWM46T1H (*(unsigned char volatile __XDATA *)0xfc90)
|
||||||
|
#define PWM46T1L (*(unsigned char volatile __XDATA *)0xfc91)
|
||||||
|
#define PWM46T2 (*(unsigned int volatile __XDATA *)0xfc92)
|
||||||
|
#define PWM46T2H (*(unsigned char volatile __XDATA *)0xfc92)
|
||||||
|
#define PWM46T2L (*(unsigned char volatile __XDATA *)0xfc93)
|
||||||
|
#define PWM46CR (*(unsigned char volatile __XDATA *)0xfc94)
|
||||||
|
#define PWM46HLD (*(unsigned char volatile __XDATA *)0xfc95)
|
||||||
|
#define PWM47T1 (*(unsigned int volatile __XDATA *)0xfc98)
|
||||||
|
#define PWM47T1H (*(unsigned char volatile __XDATA *)0xfc98)
|
||||||
|
#define PWM47T1L (*(unsigned char volatile __XDATA *)0xfc99)
|
||||||
|
#define PWM47T2 (*(unsigned int volatile __XDATA *)0xfc9a)
|
||||||
|
#define PWM47T2H (*(unsigned char volatile __XDATA *)0xfc9a)
|
||||||
|
#define PWM47T2L (*(unsigned char volatile __XDATA *)0xfc9b)
|
||||||
|
#define PWM47CR (*(unsigned char volatile __XDATA *)0xfc9c)
|
||||||
|
#define PWM47HLD (*(unsigned char volatile __XDATA *)0xfc9d)
|
||||||
|
#define PWM5C (*(unsigned int volatile __XDATA *)0xfca0)
|
||||||
|
#define PWM5CH (*(unsigned char volatile __XDATA *)0xfca0)
|
||||||
|
#define PWM5CL (*(unsigned char volatile __XDATA *)0xfca1)
|
||||||
|
#define PWM5CKS (*(unsigned char volatile __XDATA *)0xfca2)
|
||||||
|
#define PWM5IF (*(unsigned char volatile __XDATA *)0xfca5)
|
||||||
|
#define PWM5FDCR (*(unsigned char volatile __XDATA *)0xfca6)
|
||||||
|
#define PWM50T1 (*(unsigned int volatile __XDATA *)0xfcb0)
|
||||||
|
#define PWM50T1H (*(unsigned char volatile __XDATA *)0xfcb0)
|
||||||
|
#define PWM50T1L (*(unsigned char volatile __XDATA *)0xfcb1)
|
||||||
|
#define PWM50T2 (*(unsigned int volatile __XDATA *)0xfcb2)
|
||||||
|
#define PWM50T2H (*(unsigned char volatile __XDATA *)0xfcb2)
|
||||||
|
#define PWM50T2L (*(unsigned char volatile __XDATA *)0xfcb3)
|
||||||
|
#define PWM50CR (*(unsigned char volatile __XDATA *)0xfcb4)
|
||||||
|
#define PWM50HLD (*(unsigned char volatile __XDATA *)0xfcb5)
|
||||||
|
#define PWM51T1 (*(unsigned int volatile __XDATA *)0xfcb8)
|
||||||
|
#define PWM51T1H (*(unsigned char volatile __XDATA *)0xfcb8)
|
||||||
|
#define PWM51T1L (*(unsigned char volatile __XDATA *)0xfcb9)
|
||||||
|
#define PWM51T2 (*(unsigned int volatile __XDATA *)0xfcba)
|
||||||
|
#define PWM51T2H (*(unsigned char volatile __XDATA *)0xfcba)
|
||||||
|
#define PWM51T2L (*(unsigned char volatile __XDATA *)0xfcbb)
|
||||||
|
#define PWM51CR (*(unsigned char volatile __XDATA *)0xfcbc)
|
||||||
|
#define PWM51HLD (*(unsigned char volatile __XDATA *)0xfcbd)
|
||||||
|
#define PWM52T1 (*(unsigned int volatile __XDATA *)0xfcc0)
|
||||||
|
#define PWM52T1H (*(unsigned char volatile __XDATA *)0xfcc0)
|
||||||
|
#define PWM52T1L (*(unsigned char volatile __XDATA *)0xfcc1)
|
||||||
|
#define PWM52T2 (*(unsigned int volatile __XDATA *)0xfcc2)
|
||||||
|
#define PWM52T2H (*(unsigned char volatile __XDATA *)0xfcc2)
|
||||||
|
#define PWM52T2L (*(unsigned char volatile __XDATA *)0xfcc3)
|
||||||
|
#define PWM52CR (*(unsigned char volatile __XDATA *)0xfcc4)
|
||||||
|
#define PWM52HLD (*(unsigned char volatile __XDATA *)0xfcc5)
|
||||||
|
#define PWM53T1 (*(unsigned int volatile __XDATA *)0xfcc8)
|
||||||
|
#define PWM53T1H (*(unsigned char volatile __XDATA *)0xfcc8)
|
||||||
|
#define PWM53T1L (*(unsigned char volatile __XDATA *)0xfcc9)
|
||||||
|
#define PWM53T2 (*(unsigned int volatile __XDATA *)0xfcca)
|
||||||
|
#define PWM53T2H (*(unsigned char volatile __XDATA *)0xfcca)
|
||||||
|
#define PWM53T2L (*(unsigned char volatile __XDATA *)0xfccb)
|
||||||
|
#define PWM53CR (*(unsigned char volatile __XDATA *)0xfccc)
|
||||||
|
#define PWM53HLD (*(unsigned char volatile __XDATA *)0xfccd)
|
||||||
|
#define PWM54T1 (*(unsigned int volatile __XDATA *)0xfcd0)
|
||||||
|
#define PWM54T1H (*(unsigned char volatile __XDATA *)0xfcd0)
|
||||||
|
#define PWM54T1L (*(unsigned char volatile __XDATA *)0xfcd1)
|
||||||
|
#define PWM54T2 (*(unsigned int volatile __XDATA *)0xfcd2)
|
||||||
|
#define PWM54T2H (*(unsigned char volatile __XDATA *)0xfcd2)
|
||||||
|
#define PWM54T2L (*(unsigned char volatile __XDATA *)0xfcd3)
|
||||||
|
#define PWM54CR (*(unsigned char volatile __XDATA *)0xfcd4)
|
||||||
|
#define PWM54HLD (*(unsigned char volatile __XDATA *)0xfcd5)
|
||||||
|
#define PWM55T1 (*(unsigned int volatile __XDATA *)0xfcd8)
|
||||||
|
#define PWM55T1H (*(unsigned char volatile __XDATA *)0xfcd8)
|
||||||
|
#define PWM55T1L (*(unsigned char volatile __XDATA *)0xfcd9)
|
||||||
|
#define PWM55T2 (*(unsigned int volatile __XDATA *)0xfcda)
|
||||||
|
#define PWM55T2H (*(unsigned char volatile __XDATA *)0xfcda)
|
||||||
|
#define PWM55T2L (*(unsigned char volatile __XDATA *)0xfcdb)
|
||||||
|
#define PWM55CR (*(unsigned char volatile __XDATA *)0xfcdc)
|
||||||
|
#define PWM55HLD (*(unsigned char volatile __XDATA *)0xfcdd)
|
||||||
|
#define PWM56T1 (*(unsigned int volatile __XDATA *)0xfce0)
|
||||||
|
#define PWM56T1H (*(unsigned char volatile __XDATA *)0xfce0)
|
||||||
|
#define PWM56T1L (*(unsigned char volatile __XDATA *)0xfce1)
|
||||||
|
#define PWM56T2 (*(unsigned int volatile __XDATA *)0xfce2)
|
||||||
|
#define PWM56T2H (*(unsigned char volatile __XDATA *)0xfce2)
|
||||||
|
#define PWM56T2L (*(unsigned char volatile __XDATA *)0xfce3)
|
||||||
|
#define PWM56CR (*(unsigned char volatile __XDATA *)0xfce4)
|
||||||
|
#define PWM56HLD (*(unsigned char volatile __XDATA *)0xfce5)
|
||||||
|
#define PWM57T1 (*(unsigned int volatile __XDATA *)0xfce8)
|
||||||
|
#define PWM57T1H (*(unsigned char volatile __XDATA *)0xfce8)
|
||||||
|
#define PWM57T1L (*(unsigned char volatile __XDATA *)0xfce9)
|
||||||
|
#define PWM57T2 (*(unsigned int volatile __XDATA *)0xfcea)
|
||||||
|
#define PWM57T2H (*(unsigned char volatile __XDATA *)0xfcea)
|
||||||
|
#define PWM57T2L (*(unsigned char volatile __XDATA *)0xfceb)
|
||||||
|
#define PWM57CR (*(unsigned char volatile __XDATA *)0xfcec)
|
||||||
|
#define PWM57HLD (*(unsigned char volatile __XDATA *)0xfced)
|
||||||
|
|
||||||
|
#define MD3 (*(unsigned char volatile __XDATA *)0xfcf0)
|
||||||
|
#define MD2 (*(unsigned char volatile __XDATA *)0xfcf1)
|
||||||
|
#define MD1 (*(unsigned char volatile __XDATA *)0xfcf2)
|
||||||
|
#define MD0 (*(unsigned char volatile __XDATA *)0xfcf3)
|
||||||
|
#define MD5 (*(unsigned char volatile __XDATA *)0xfcf4)
|
||||||
|
#define MD4 (*(unsigned char volatile __XDATA *)0xfcf5)
|
||||||
|
#define ARCON (*(unsigned char volatile __XDATA *)0xfcf6)
|
||||||
|
#define OPCON (*(unsigned char volatile __XDATA *)0xfcf7)
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FB00H-FBFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define COMEN (*(unsigned char volatile __XDATA *)0xfb00)
|
||||||
|
#define SEGENL (*(unsigned char volatile __XDATA *)0xfb01)
|
||||||
|
#define SEGENH (*(unsigned char volatile __XDATA *)0xfb02)
|
||||||
|
#define LEDCTRL (*(unsigned char volatile __XDATA *)0xfb03)
|
||||||
|
#define LEDCKS (*(unsigned char volatile __XDATA *)0xfb04)
|
||||||
|
#define COM0_DA_L (*(unsigned char volatile __XDATA *)0xfb10)
|
||||||
|
#define COM1_DA_L (*(unsigned char volatile __XDATA *)0xfb11)
|
||||||
|
#define COM2_DA_L (*(unsigned char volatile __XDATA *)0xfb12)
|
||||||
|
#define COM3_DA_L (*(unsigned char volatile __XDATA *)0xfb13)
|
||||||
|
#define COM4_DA_L (*(unsigned char volatile __XDATA *)0xfb14)
|
||||||
|
#define COM5_DA_L (*(unsigned char volatile __XDATA *)0xfb15)
|
||||||
|
#define COM6_DA_L (*(unsigned char volatile __XDATA *)0xfb16)
|
||||||
|
#define COM7_DA_L (*(unsigned char volatile __XDATA *)0xfb17)
|
||||||
|
#define COM0_DA_H (*(unsigned char volatile __XDATA *)0xfb18)
|
||||||
|
#define COM1_DA_H (*(unsigned char volatile __XDATA *)0xfb19)
|
||||||
|
#define COM2_DA_H (*(unsigned char volatile __XDATA *)0xfb1a)
|
||||||
|
#define COM3_DA_H (*(unsigned char volatile __XDATA *)0xfb1b)
|
||||||
|
#define COM4_DA_H (*(unsigned char volatile __XDATA *)0xfb1c)
|
||||||
|
#define COM5_DA_H (*(unsigned char volatile __XDATA *)0xfb1d)
|
||||||
|
#define COM6_DA_H (*(unsigned char volatile __XDATA *)0xfb1e)
|
||||||
|
#define COM7_DA_H (*(unsigned char volatile __XDATA *)0xfb1f)
|
||||||
|
#define COM0_DC_L (*(unsigned char volatile __XDATA *)0xfb20)
|
||||||
|
#define COM1_DC_L (*(unsigned char volatile __XDATA *)0xfb21)
|
||||||
|
#define COM2_DC_L (*(unsigned char volatile __XDATA *)0xfb22)
|
||||||
|
#define COM3_DC_L (*(unsigned char volatile __XDATA *)0xfb23)
|
||||||
|
#define COM4_DC_L (*(unsigned char volatile __XDATA *)0xfb24)
|
||||||
|
#define COM5_DC_L (*(unsigned char volatile __XDATA *)0xfb25)
|
||||||
|
#define COM6_DC_L (*(unsigned char volatile __XDATA *)0xfb26)
|
||||||
|
#define COM7_DC_L (*(unsigned char volatile __XDATA *)0xfb27)
|
||||||
|
#define COM0_DC_H (*(unsigned char volatile __XDATA *)0xfb28)
|
||||||
|
#define COM1_DC_H (*(unsigned char volatile __XDATA *)0xfb29)
|
||||||
|
#define COM2_DC_H (*(unsigned char volatile __XDATA *)0xfb2a)
|
||||||
|
#define COM3_DC_H (*(unsigned char volatile __XDATA *)0xfb2b)
|
||||||
|
#define COM4_DC_H (*(unsigned char volatile __XDATA *)0xfb2c)
|
||||||
|
#define COM5_DC_H (*(unsigned char volatile __XDATA *)0xfb2d)
|
||||||
|
#define COM6_DC_H (*(unsigned char volatile __XDATA *)0xfb2e)
|
||||||
|
#define COM7_DC_H (*(unsigned char volatile __XDATA *)0xfb2f)
|
||||||
|
|
||||||
|
#define TSCHEN1 (*(unsigned char volatile __XDATA *)0xfb40)
|
||||||
|
#define TSCHEN2 (*(unsigned char volatile __XDATA *)0xfb41)
|
||||||
|
#define TSCFG1 (*(unsigned char volatile __XDATA *)0xfb42)
|
||||||
|
#define TSCFG2 (*(unsigned char volatile __XDATA *)0xfb43)
|
||||||
|
#define TSWUTC (*(unsigned char volatile __XDATA *)0xfb44)
|
||||||
|
#define TSCTRL (*(unsigned char volatile __XDATA *)0xfb45)
|
||||||
|
#define TSSTA1 (*(unsigned char volatile __XDATA *)0xfb46)
|
||||||
|
#define TSSTA2 (*(unsigned char volatile __XDATA *)0xfb47)
|
||||||
|
#define TSRT (*(unsigned char volatile __XDATA *)0xfb48)
|
||||||
|
#define TSDAT (*(unsigned int volatile __XDATA *)0xfb49)
|
||||||
|
#define TSDATH (*(unsigned char volatile __XDATA *)0xfb49)
|
||||||
|
#define TSDATL (*(unsigned char volatile __XDATA *)0xfb4a)
|
||||||
|
#define TSTH00 (*(unsigned int volatile __XDATA *)0xfb50)
|
||||||
|
#define TSTH00H (*(unsigned char volatile __XDATA *)0xfb50)
|
||||||
|
#define TSTH00L (*(unsigned char volatile __XDATA *)0xfb51)
|
||||||
|
#define TSTH01 (*(unsigned int volatile __XDATA *)0xfb52)
|
||||||
|
#define TSTH01H (*(unsigned char volatile __XDATA *)0xfb52)
|
||||||
|
#define TSTH01L (*(unsigned char volatile __XDATA *)0xfb53)
|
||||||
|
#define TSTH02 (*(unsigned int volatile __XDATA *)0xfb54)
|
||||||
|
#define TSTH02H (*(unsigned char volatile __XDATA *)0xfb54)
|
||||||
|
#define TSTH02L (*(unsigned char volatile __XDATA *)0xfb55)
|
||||||
|
#define TSTH03 (*(unsigned int volatile __XDATA *)0xfb56)
|
||||||
|
#define TSTH03H (*(unsigned char volatile __XDATA *)0xfb56)
|
||||||
|
#define TSTH03L (*(unsigned char volatile __XDATA *)0xfb57)
|
||||||
|
#define TSTH04 (*(unsigned int volatile __XDATA *)0xfb58)
|
||||||
|
#define TSTH04H (*(unsigned char volatile __XDATA *)0xfb58)
|
||||||
|
#define TSTH04L (*(unsigned char volatile __XDATA *)0xfb59)
|
||||||
|
#define TSTH05 (*(unsigned int volatile __XDATA *)0xfb5a)
|
||||||
|
#define TSTH05H (*(unsigned char volatile __XDATA *)0xfb5a)
|
||||||
|
#define TSTH05L (*(unsigned char volatile __XDATA *)0xfb5b)
|
||||||
|
#define TSTH06 (*(unsigned int volatile __XDATA *)0xfb5c)
|
||||||
|
#define TSTH06H (*(unsigned char volatile __XDATA *)0xfb5c)
|
||||||
|
#define TSTH06L (*(unsigned char volatile __XDATA *)0xfb5d)
|
||||||
|
#define TSTH07 (*(unsigned int volatile __XDATA *)0xfb5e)
|
||||||
|
#define TSTH07H (*(unsigned char volatile __XDATA *)0xfb5e)
|
||||||
|
#define TSTH07L (*(unsigned char volatile __XDATA *)0xfb5f)
|
||||||
|
#define TSTH08 (*(unsigned int volatile __XDATA *)0xfb60)
|
||||||
|
#define TSTH08H (*(unsigned char volatile __XDATA *)0xfb60)
|
||||||
|
#define TSTH08L (*(unsigned char volatile __XDATA *)0xfb61)
|
||||||
|
#define TSTH09 (*(unsigned int volatile __XDATA *)0xfb62)
|
||||||
|
#define TSTH09H (*(unsigned char volatile __XDATA *)0xfb62)
|
||||||
|
#define TSTH09L (*(unsigned char volatile __XDATA *)0xfb63)
|
||||||
|
#define TSTH10 (*(unsigned int volatile __XDATA *)0xfb64)
|
||||||
|
#define TSTH10H (*(unsigned char volatile __XDATA *)0xfb64)
|
||||||
|
#define TSTH10L (*(unsigned char volatile __XDATA *)0xfb65)
|
||||||
|
#define TSTH11 (*(unsigned int volatile __XDATA *)0xfb66)
|
||||||
|
#define TSTH11H (*(unsigned char volatile __XDATA *)0xfb66)
|
||||||
|
#define TSTH11L (*(unsigned char volatile __XDATA *)0xfb67)
|
||||||
|
#define TSTH12 (*(unsigned int volatile __XDATA *)0xfb68)
|
||||||
|
#define TSTH12H (*(unsigned char volatile __XDATA *)0xfb68)
|
||||||
|
#define TSTH12L (*(unsigned char volatile __XDATA *)0xfb69)
|
||||||
|
#define TSTH13 (*(unsigned int volatile __XDATA *)0xfb6a)
|
||||||
|
#define TSTH13H (*(unsigned char volatile __XDATA *)0xfb6a)
|
||||||
|
#define TSTH13L (*(unsigned char volatile __XDATA *)0xfb6b)
|
||||||
|
#define TSTH14 (*(unsigned int volatile __XDATA *)0xfb6c)
|
||||||
|
#define TSTH14H (*(unsigned char volatile __XDATA *)0xfb6c)
|
||||||
|
#define TSTH14L (*(unsigned char volatile __XDATA *)0xfb6d)
|
||||||
|
#define TSTH15 (*(unsigned int volatile __XDATA *)0xfb6e)
|
||||||
|
#define TSTH15H (*(unsigned char volatile __XDATA *)0xfb6e)
|
||||||
|
#define TSTH15L (*(unsigned char volatile __XDATA *)0xfb6f)
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FA00H-FAFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
492
include/fw_reg_stc8h.h
Normal file
492
include/fw_reg_stc8h.h
Normal file
@ -0,0 +1,492 @@
|
|||||||
|
#ifndef __IO_REG_STC8H_H__
|
||||||
|
#define __IO_REG_STC8H_H__
|
||||||
|
|
||||||
|
#include "fw_reg_base.h"
|
||||||
|
|
||||||
|
SFR(USBCLK, 0xDC);
|
||||||
|
|
||||||
|
SFR(ADCCFG, 0xDE);
|
||||||
|
SFR(IP3, 0xDF);
|
||||||
|
|
||||||
|
SFR(ACC, 0xE0);
|
||||||
|
SFR(P7M1, 0xE1);
|
||||||
|
SFR(P7M0, 0xE2);
|
||||||
|
SFR(DPS, 0xE3);
|
||||||
|
SFR(DPL1, 0xE4);
|
||||||
|
SFR(DPH1, 0xE5);
|
||||||
|
SFR(CMPCR1, 0xE6);
|
||||||
|
SFR(CMPCR2, 0xE7);
|
||||||
|
SFR(P6, 0xE8);
|
||||||
|
SFR(USBDAT, 0xEC);
|
||||||
|
SFR(IP3H, 0xEE);
|
||||||
|
SFR(AUXINTIF, 0xEF);
|
||||||
|
SFR(B, 0xF0);
|
||||||
|
|
||||||
|
SFR(USBCON, 0xF4);
|
||||||
|
|
||||||
|
SFR(IAP_TPS, 0xF5);
|
||||||
|
|
||||||
|
SFR(P7, 0xF8);
|
||||||
|
SFR(USBADR, 0xFC);
|
||||||
|
|
||||||
|
SFR(RSTCFG, 0xFF);
|
||||||
|
|
||||||
|
|
||||||
|
//如下特殊功能寄存器位于扩展RAM区域
|
||||||
|
//访问这些寄存器,需先将P_SW2的BIT7设置为1,才可正常读写
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FF00H-FFFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FE00H-FEFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define CKSEL (*(unsigned char volatile __XDATA *)0xfe00)
|
||||||
|
#define CLKDIV (*(unsigned char volatile __XDATA *)0xfe01)
|
||||||
|
#define HIRCCR (*(unsigned char volatile __XDATA *)0xfe02)
|
||||||
|
#define XOSCCR (*(unsigned char volatile __XDATA *)0xfe03)
|
||||||
|
#define IRC32KCR (*(unsigned char volatile __XDATA *)0xfe04)
|
||||||
|
#define MCLKOCR (*(unsigned char volatile __XDATA *)0xfe05)
|
||||||
|
#define IRCDB (*(unsigned char volatile __XDATA *)0xfe06)
|
||||||
|
#define X32KCR (*(unsigned char volatile __XDATA *)0xfe08)
|
||||||
|
#define PxPU 0xfe10
|
||||||
|
#define P0PU SFRX(PxPU + 0)
|
||||||
|
#define P1PU SFRX(PxPU + 1)
|
||||||
|
#define P2PU (*(unsigned char volatile __XDATA *)0xfe12)
|
||||||
|
#define P3PU (*(unsigned char volatile __XDATA *)0xfe13)
|
||||||
|
#define P4PU (*(unsigned char volatile __XDATA *)0xfe14)
|
||||||
|
#define P5PU (*(unsigned char volatile __XDATA *)0xfe15)
|
||||||
|
#define P6PU (*(unsigned char volatile __XDATA *)0xfe16)
|
||||||
|
#define P7PU (*(unsigned char volatile __XDATA *)0xfe17)
|
||||||
|
#define PxNCS 0xfe18
|
||||||
|
#define P0NCS (*(unsigned char volatile __XDATA *)0xfe18)
|
||||||
|
#define P1NCS (*(unsigned char volatile __XDATA *)0xfe19)
|
||||||
|
#define P2NCS (*(unsigned char volatile __XDATA *)0xfe1a)
|
||||||
|
#define P3NCS (*(unsigned char volatile __XDATA *)0xfe1b)
|
||||||
|
#define P4NCS (*(unsigned char volatile __XDATA *)0xfe1c)
|
||||||
|
#define P5NCS (*(unsigned char volatile __XDATA *)0xfe1d)
|
||||||
|
#define P6NCS (*(unsigned char volatile __XDATA *)0xfe1e)
|
||||||
|
#define P7NCS (*(unsigned char volatile __XDATA *)0xfe1f)
|
||||||
|
#define PxSR 0xfe20
|
||||||
|
#define P0SR (*(unsigned char volatile __XDATA *)0xfe20)
|
||||||
|
#define P1SR (*(unsigned char volatile __XDATA *)0xfe21)
|
||||||
|
#define P2SR (*(unsigned char volatile __XDATA *)0xfe22)
|
||||||
|
#define P3SR (*(unsigned char volatile __XDATA *)0xfe23)
|
||||||
|
#define P4SR (*(unsigned char volatile __XDATA *)0xfe24)
|
||||||
|
#define P5SR (*(unsigned char volatile __XDATA *)0xfe25)
|
||||||
|
#define P6SR (*(unsigned char volatile __XDATA *)0xfe26)
|
||||||
|
#define P7SR (*(unsigned char volatile __XDATA *)0xfe27)
|
||||||
|
#define PxDR 0xfe28
|
||||||
|
#define P0DR (*(unsigned char volatile __XDATA *)0xfe28)
|
||||||
|
#define P1DR (*(unsigned char volatile __XDATA *)0xfe29)
|
||||||
|
#define P2DR (*(unsigned char volatile __XDATA *)0xfe2a)
|
||||||
|
#define P3DR (*(unsigned char volatile __XDATA *)0xfe2b)
|
||||||
|
#define P4DR (*(unsigned char volatile __XDATA *)0xfe2c)
|
||||||
|
#define P5DR (*(unsigned char volatile __XDATA *)0xfe2d)
|
||||||
|
#define P6DR (*(unsigned char volatile __XDATA *)0xfe2e)
|
||||||
|
#define P7DR (*(unsigned char volatile __XDATA *)0xfe2f)
|
||||||
|
#define PxIE 0xfe30
|
||||||
|
#define P0IE (*(unsigned char volatile __XDATA *)0xfe30)
|
||||||
|
#define P1IE (*(unsigned char volatile __XDATA *)0xfe31)
|
||||||
|
#define P2IE (*(unsigned char volatile __XDATA *)0xfe32)
|
||||||
|
#define P3IE (*(unsigned char volatile __XDATA *)0xfe33)
|
||||||
|
#define P4IE (*(unsigned char volatile __XDATA *)0xfe34)
|
||||||
|
#define P5IE (*(unsigned char volatile __XDATA *)0xfe35)
|
||||||
|
#define P6IE (*(unsigned char volatile __XDATA *)0xfe36)
|
||||||
|
#define P7IE (*(unsigned char volatile __XDATA *)0xfe37)
|
||||||
|
#define LCMIFCFG (*(unsigned char volatile __XDATA *)0xfe50)
|
||||||
|
#define RTCCR (*(unsigned char volatile __XDATA *)0xfe60)
|
||||||
|
#define RTCCFG (*(unsigned char volatile __XDATA *)0xfe61)
|
||||||
|
#define RTCIEN (*(unsigned char volatile __XDATA *)0xfe62)
|
||||||
|
#define RTCIF (*(unsigned char volatile __XDATA *)0xfe63)
|
||||||
|
#define ALAHOUR (*(unsigned char volatile __XDATA *)0xfe64)
|
||||||
|
#define ALAMIN (*(unsigned char volatile __XDATA *)0xfe65)
|
||||||
|
#define ALASEC (*(unsigned char volatile __XDATA *)0xfe66)
|
||||||
|
#define ALASSEC (*(unsigned char volatile __XDATA *)0xfe67)
|
||||||
|
#define INIYEAR (*(unsigned char volatile __XDATA *)0xfe68)
|
||||||
|
#define INIMONTH (*(unsigned char volatile __XDATA *)0xfe69)
|
||||||
|
#define INIDAY (*(unsigned char volatile __XDATA *)0xfe6a)
|
||||||
|
#define INIHOUR (*(unsigned char volatile __XDATA *)0xfe6b)
|
||||||
|
#define INIMIN (*(unsigned char volatile __XDATA *)0xfe6c)
|
||||||
|
#define INISEC (*(unsigned char volatile __XDATA *)0xfe6d)
|
||||||
|
#define INISSEC (*(unsigned char volatile __XDATA *)0xfe6e)
|
||||||
|
#define YEAR (*(unsigned char volatile __XDATA *)0xfe70)
|
||||||
|
#define MONTH (*(unsigned char volatile __XDATA *)0xfe71)
|
||||||
|
#define DAY (*(unsigned char volatile __XDATA *)0xfe72)
|
||||||
|
#define HOUR (*(unsigned char volatile __XDATA *)0xfe73)
|
||||||
|
#define MIN (*(unsigned char volatile __XDATA *)0xfe74)
|
||||||
|
#define SEC (*(unsigned char volatile __XDATA *)0xfe75)
|
||||||
|
#define SSEC (*(unsigned char volatile __XDATA *)0xfe76)
|
||||||
|
|
||||||
|
#define I2CCFG (*(unsigned char volatile __XDATA *)0xfe80)
|
||||||
|
#define I2CMSCR (*(unsigned char volatile __XDATA *)0xfe81)
|
||||||
|
#define I2CMSST (*(unsigned char volatile __XDATA *)0xfe82)
|
||||||
|
#define I2CSLCR (*(unsigned char volatile __XDATA *)0xfe83)
|
||||||
|
#define I2CSLST (*(unsigned char volatile __XDATA *)0xfe84)
|
||||||
|
#define I2CSLADR (*(unsigned char volatile __XDATA *)0xfe85)
|
||||||
|
#define I2CTXD (*(unsigned char volatile __XDATA *)0xfe86)
|
||||||
|
#define I2CRXD (*(unsigned char volatile __XDATA *)0xfe87)
|
||||||
|
#define I2CMSAUX (*(unsigned char volatile __XDATA *)0xfe88)
|
||||||
|
|
||||||
|
#define TM2PS (*(unsigned char volatile __XDATA *)0xfea2)
|
||||||
|
#define TM3PS (*(unsigned char volatile __XDATA *)0xfea3)
|
||||||
|
#define TM4PS (*(unsigned char volatile __XDATA *)0xfea4)
|
||||||
|
#define ADCTIM (*(unsigned char volatile __XDATA *)0xfea8)
|
||||||
|
|
||||||
|
#define PWM1_ETRPS (*(unsigned char volatile __XDATA *)0xfeb0)
|
||||||
|
#define PWM1_ENO (*(unsigned char volatile __XDATA *)0xfeb1)
|
||||||
|
#define PWM1_PS (*(unsigned char volatile __XDATA *)0xfeb2)
|
||||||
|
#define PWM1_IOAUX (*(unsigned char volatile __XDATA *)0xfeb3)
|
||||||
|
#define PWM2_ETRPS (*(unsigned char volatile __XDATA *)0xfeb4)
|
||||||
|
#define PWM2_ENO (*(unsigned char volatile __XDATA *)0xfeb5)
|
||||||
|
#define PWM2_PS (*(unsigned char volatile __XDATA *)0xfeb6)
|
||||||
|
#define PWM2_IOAUX (*(unsigned char volatile __XDATA *)0xfeb7)
|
||||||
|
#define PWM1_CR1 (*(unsigned char volatile __XDATA *)0xfec0)
|
||||||
|
#define PWM1_CR2 (*(unsigned char volatile __XDATA *)0xfec1)
|
||||||
|
#define PWM1_SMCR (*(unsigned char volatile __XDATA *)0xfec2)
|
||||||
|
#define PWM1_ETR (*(unsigned char volatile __XDATA *)0xfec3)
|
||||||
|
#define PWM1_IER (*(unsigned char volatile __XDATA *)0xfec4)
|
||||||
|
#define PWM1_SR1 (*(unsigned char volatile __XDATA *)0xfec5)
|
||||||
|
#define PWM1_SR2 (*(unsigned char volatile __XDATA *)0xfec6)
|
||||||
|
#define PWM1_EGR (*(unsigned char volatile __XDATA *)0xfec7)
|
||||||
|
#define PWM1_CCMR1 (*(unsigned char volatile __XDATA *)0xfec8)
|
||||||
|
#define PWM1_CCMR2 (*(unsigned char volatile __XDATA *)0xfec9)
|
||||||
|
#define PWM1_CCMR3 (*(unsigned char volatile __XDATA *)0xfeca)
|
||||||
|
#define PWM1_CCMR4 (*(unsigned char volatile __XDATA *)0xfecb)
|
||||||
|
#define PWM1_CCER1 (*(unsigned char volatile __XDATA *)0xfecc)
|
||||||
|
#define PWM1_CCER2 (*(unsigned char volatile __XDATA *)0xfecd)
|
||||||
|
#define PWM1_CNTR (*(unsigned int volatile __XDATA *)0xfece)
|
||||||
|
#define PWM1_CNTRH (*(unsigned char volatile __XDATA *)0xfece)
|
||||||
|
#define PWM1_CNTRL (*(unsigned char volatile __XDATA *)0xfecf)
|
||||||
|
#define PWM1_PSCR (*(unsigned int volatile __XDATA *)0xfed0)
|
||||||
|
#define PWM1_PSCRH (*(unsigned char volatile __XDATA *)0xfed0)
|
||||||
|
#define PWM1_PSCRL (*(unsigned char volatile __XDATA *)0xfed1)
|
||||||
|
#define PWM1_ARR (*(unsigned int volatile __XDATA *)0xfed2)
|
||||||
|
#define PWM1_ARRH (*(unsigned char volatile __XDATA *)0xfed2)
|
||||||
|
#define PWM1_ARRL (*(unsigned char volatile __XDATA *)0xfed3)
|
||||||
|
#define PWM1_RCR (*(unsigned char volatile __XDATA *)0xfed4)
|
||||||
|
#define PWM1_CCR1 (*(unsigned int volatile __XDATA *)0xfed5)
|
||||||
|
#define PWM1_CCR1H (*(unsigned char volatile __XDATA *)0xfed5)
|
||||||
|
#define PWM1_CCR1L (*(unsigned char volatile __XDATA *)0xfed6)
|
||||||
|
#define PWM1_CCR2 (*(unsigned int volatile __XDATA *)0xfed7)
|
||||||
|
#define PWM1_CCR2H (*(unsigned char volatile __XDATA *)0xfed7)
|
||||||
|
#define PWM1_CCR2L (*(unsigned char volatile __XDATA *)0xfed8)
|
||||||
|
#define PWM1_CCR3 (*(unsigned int volatile __XDATA *)0xfed9)
|
||||||
|
#define PWM1_CCR3H (*(unsigned char volatile __XDATA *)0xfed9)
|
||||||
|
#define PWM1_CCR3L (*(unsigned char volatile __XDATA *)0xfeda)
|
||||||
|
#define PWM1_CCR4 (*(unsigned int volatile __XDATA *)0xfedb)
|
||||||
|
#define PWM1_CCR4H (*(unsigned char volatile __XDATA *)0xfedb)
|
||||||
|
#define PWM1_CCR4L (*(unsigned char volatile __XDATA *)0xfedc)
|
||||||
|
#define PWM1_BKR (*(unsigned char volatile __XDATA *)0xfedd)
|
||||||
|
#define PWM1_DTR (*(unsigned char volatile __XDATA *)0xfede)
|
||||||
|
#define PWM1_OISR (*(unsigned char volatile __XDATA *)0xfedf)
|
||||||
|
#define PWM2_CR1 (*(unsigned char volatile __XDATA *)0xfee0)
|
||||||
|
#define PWM2_CR2 (*(unsigned char volatile __XDATA *)0xfee1)
|
||||||
|
#define PWM2_SMCR (*(unsigned char volatile __XDATA *)0xfee2)
|
||||||
|
#define PWM2_ETR (*(unsigned char volatile __XDATA *)0xfee3)
|
||||||
|
#define PWM2_IER (*(unsigned char volatile __XDATA *)0xfee4)
|
||||||
|
#define PWM2_SR1 (*(unsigned char volatile __XDATA *)0xfee5)
|
||||||
|
#define PWM2_SR2 (*(unsigned char volatile __XDATA *)0xfee6)
|
||||||
|
#define PWM2_EGR (*(unsigned char volatile __XDATA *)0xfee7)
|
||||||
|
#define PWM2_CCMR1 (*(unsigned char volatile __XDATA *)0xfee8)
|
||||||
|
#define PWM2_CCMR2 (*(unsigned char volatile __XDATA *)0xfee9)
|
||||||
|
#define PWM2_CCMR3 (*(unsigned char volatile __XDATA *)0xfeea)
|
||||||
|
#define PWM2_CCMR4 (*(unsigned char volatile __XDATA *)0xfeeb)
|
||||||
|
#define PWM2_CCER1 (*(unsigned char volatile __XDATA *)0xfeec)
|
||||||
|
#define PWM2_CCER2 (*(unsigned char volatile __XDATA *)0xfeed)
|
||||||
|
#define PWM2_CNTR (*(unsigned int volatile __XDATA *)0xfeee)
|
||||||
|
#define PWM2_CNTRH (*(unsigned char volatile __XDATA *)0xfeee)
|
||||||
|
#define PWM2_CNTRL (*(unsigned char volatile __XDATA *)0xfeef)
|
||||||
|
#define PWM2_PSCR (*(unsigned int volatile __XDATA *)0xfef0)
|
||||||
|
#define PWM2_PSCRH (*(unsigned char volatile __XDATA *)0xfef0)
|
||||||
|
#define PWM2_PSCRL (*(unsigned char volatile __XDATA *)0xfef1)
|
||||||
|
#define PWM2_ARR (*(unsigned int volatile __XDATA *)0xfef2)
|
||||||
|
#define PWM2_ARRH (*(unsigned char volatile __XDATA *)0xfef2)
|
||||||
|
#define PWM2_ARRL (*(unsigned char volatile __XDATA *)0xfef3)
|
||||||
|
#define PWM2_RCR (*(unsigned char volatile __XDATA *)0xfef4)
|
||||||
|
#define PWM2_CCR1 (*(unsigned int volatile __XDATA *)0xfef5)
|
||||||
|
#define PWM2_CCR1H (*(unsigned char volatile __XDATA *)0xfef5)
|
||||||
|
#define PWM2_CCR1L (*(unsigned char volatile __XDATA *)0xfef6)
|
||||||
|
#define PWM2_CCR2 (*(unsigned int volatile __XDATA *)0xfef7)
|
||||||
|
#define PWM2_CCR2H (*(unsigned char volatile __XDATA *)0xfef7)
|
||||||
|
#define PWM2_CCR2L (*(unsigned char volatile __XDATA *)0xfef8)
|
||||||
|
#define PWM2_CCR3 (*(unsigned int volatile __XDATA *)0xfef9)
|
||||||
|
#define PWM2_CCR3H (*(unsigned char volatile __XDATA *)0xfef9)
|
||||||
|
#define PWM2_CCR3L (*(unsigned char volatile __XDATA *)0xfefa)
|
||||||
|
#define PWM2_CCR4 (*(unsigned int volatile __XDATA *)0xfefb)
|
||||||
|
#define PWM2_CCR4H (*(unsigned char volatile __XDATA *)0xfefb)
|
||||||
|
#define PWM2_CCR4L (*(unsigned char volatile __XDATA *)0xfefc)
|
||||||
|
#define PWM2_BKR (*(unsigned char volatile __XDATA *)0xfefd)
|
||||||
|
#define PWM2_DTR (*(unsigned char volatile __XDATA *)0xfefe)
|
||||||
|
#define PWM2_OISR (*(unsigned char volatile __XDATA *)0xfeff)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* suppress xdata space memory overlap
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
#define PWMA_ETRPS (*(unsigned char volatile __XDATA *)0xfeb0)
|
||||||
|
#define PWMA_ENO (*(unsigned char volatile __XDATA *)0xfeb1)
|
||||||
|
#define PWMA_PS (*(unsigned char volatile __XDATA *)0xfeb2)
|
||||||
|
#define PWMA_IOAUX (*(unsigned char volatile __XDATA *)0xfeb3)
|
||||||
|
#define PWMB_ETRPS (*(unsigned char volatile __XDATA *)0xfeb4)
|
||||||
|
#define PWMB_ENO (*(unsigned char volatile __XDATA *)0xfeb5)
|
||||||
|
#define PWMB_PS (*(unsigned char volatile __XDATA *)0xfeb6)
|
||||||
|
#define PWMB_IOAUX (*(unsigned char volatile __XDATA *)0xfeb7)
|
||||||
|
#define PWMA_CR1 (*(unsigned char volatile __XDATA *)0xfec0)
|
||||||
|
#define PWMA_CR2 (*(unsigned char volatile __XDATA *)0xfec1)
|
||||||
|
#define PWMA_SMCR (*(unsigned char volatile __XDATA *)0xfec2)
|
||||||
|
#define PWMA_ETR (*(unsigned char volatile __XDATA *)0xfec3)
|
||||||
|
#define PWMA_IER (*(unsigned char volatile __XDATA *)0xfec4)
|
||||||
|
#define PWMA_SR1 (*(unsigned char volatile __XDATA *)0xfec5)
|
||||||
|
#define PWMA_SR2 (*(unsigned char volatile __XDATA *)0xfec6)
|
||||||
|
#define PWMA_EGR (*(unsigned char volatile __XDATA *)0xfec7)
|
||||||
|
#define PWMA_CCMR1 (*(unsigned char volatile __XDATA *)0xfec8)
|
||||||
|
#define PWMA_CCMR2 (*(unsigned char volatile __XDATA *)0xfec9)
|
||||||
|
#define PWMA_CCMR3 (*(unsigned char volatile __XDATA *)0xfeca)
|
||||||
|
#define PWMA_CCMR4 (*(unsigned char volatile __XDATA *)0xfecb)
|
||||||
|
#define PWMA_CCER1 (*(unsigned char volatile __XDATA *)0xfecc)
|
||||||
|
#define PWMA_CCER2 (*(unsigned char volatile __XDATA *)0xfecd)
|
||||||
|
#define PWMA_CNTR (*(unsigned int volatile __XDATA *)0xfece)
|
||||||
|
#define PWMA_CNTRH (*(unsigned char volatile __XDATA *)0xfece)
|
||||||
|
#define PWMA_CNTRL (*(unsigned char volatile __XDATA *)0xfecf)
|
||||||
|
#define PWMA_PSCR (*(unsigned int volatile __XDATA *)0xfed0)
|
||||||
|
#define PWMA_PSCRH (*(unsigned char volatile __XDATA *)0xfed0)
|
||||||
|
#define PWMA_PSCRL (*(unsigned char volatile __XDATA *)0xfed1)
|
||||||
|
#define PWMA_ARR (*(unsigned int volatile __XDATA *)0xfed2)
|
||||||
|
#define PWMA_ARRH (*(unsigned char volatile __XDATA *)0xfed2)
|
||||||
|
#define PWMA_ARRL (*(unsigned char volatile __XDATA *)0xfed3)
|
||||||
|
#define PWMA_RCR (*(unsigned char volatile __XDATA *)0xfed4)
|
||||||
|
#define PWMA_CCR1 (*(unsigned int volatile __XDATA *)0xfed5)
|
||||||
|
#define PWMA_CCR1H (*(unsigned char volatile __XDATA *)0xfed5)
|
||||||
|
#define PWMA_CCR1L (*(unsigned char volatile __XDATA *)0xfed6)
|
||||||
|
#define PWMA_CCR2 (*(unsigned int volatile __XDATA *)0xfed7)
|
||||||
|
#define PWMA_CCR2H (*(unsigned char volatile __XDATA *)0xfed7)
|
||||||
|
#define PWMA_CCR2L (*(unsigned char volatile __XDATA *)0xfed8)
|
||||||
|
#define PWMA_CCR3 (*(unsigned int volatile __XDATA *)0xfed9)
|
||||||
|
#define PWMA_CCR3H (*(unsigned char volatile __XDATA *)0xfed9)
|
||||||
|
#define PWMA_CCR3L (*(unsigned char volatile __XDATA *)0xfeda)
|
||||||
|
#define PWMA_CCR4 (*(unsigned int volatile __XDATA *)0xfedb)
|
||||||
|
#define PWMA_CCR4H (*(unsigned char volatile __XDATA *)0xfedb)
|
||||||
|
#define PWMA_CCR4L (*(unsigned char volatile __XDATA *)0xfedc)
|
||||||
|
#define PWMA_BKR (*(unsigned char volatile __XDATA *)0xfedd)
|
||||||
|
#define PWMA_DTR (*(unsigned char volatile __XDATA *)0xfede)
|
||||||
|
#define PWMA_OISR (*(unsigned char volatile __XDATA *)0xfedf)
|
||||||
|
#define PWMB_CR1 (*(unsigned char volatile __XDATA *)0xfee0)
|
||||||
|
#define PWMB_CR2 (*(unsigned char volatile __XDATA *)0xfee1)
|
||||||
|
#define PWMB_SMCR (*(unsigned char volatile __XDATA *)0xfee2)
|
||||||
|
#define PWMB_ETR (*(unsigned char volatile __XDATA *)0xfee3)
|
||||||
|
#define PWMB_IER (*(unsigned char volatile __XDATA *)0xfee4)
|
||||||
|
#define PWMB_SR1 (*(unsigned char volatile __XDATA *)0xfee5)
|
||||||
|
#define PWMB_SR2 (*(unsigned char volatile __XDATA *)0xfee6)
|
||||||
|
#define PWMB_EGR (*(unsigned char volatile __XDATA *)0xfee7)
|
||||||
|
#define PWMB_CCMR1 (*(unsigned char volatile __XDATA *)0xfee8)
|
||||||
|
#define PWMB_CCMR2 (*(unsigned char volatile __XDATA *)0xfee9)
|
||||||
|
#define PWMB_CCMR3 (*(unsigned char volatile __XDATA *)0xfeea)
|
||||||
|
#define PWMB_CCMR4 (*(unsigned char volatile __XDATA *)0xfeeb)
|
||||||
|
#define PWMB_CCER1 (*(unsigned char volatile __XDATA *)0xfeec)
|
||||||
|
#define PWMB_CCER2 (*(unsigned char volatile __XDATA *)0xfeed)
|
||||||
|
#define PWMB_CNTR (*(unsigned int volatile __XDATA *)0xfeee)
|
||||||
|
#define PWMB_CNTRH (*(unsigned char volatile __XDATA *)0xfeee)
|
||||||
|
#define PWMB_CNTRL (*(unsigned char volatile __XDATA *)0xfeef)
|
||||||
|
#define PWMB_PSCR (*(unsigned int volatile __XDATA *)0xfef0)
|
||||||
|
#define PWMB_PSCRH (*(unsigned char volatile __XDATA *)0xfef0)
|
||||||
|
#define PWMB_PSCRL (*(unsigned char volatile __XDATA *)0xfef1)
|
||||||
|
#define PWMB_ARR (*(unsigned int volatile __XDATA *)0xfef2)
|
||||||
|
#define PWMB_ARRH (*(unsigned char volatile __XDATA *)0xfef2)
|
||||||
|
#define PWMB_ARRL (*(unsigned char volatile __XDATA *)0xfef3)
|
||||||
|
#define PWMB_RCR (*(unsigned char volatile __XDATA *)0xfef4)
|
||||||
|
#define PWMB_CCR5 (*(unsigned int volatile __XDATA *)0xfef5)
|
||||||
|
#define PWMB_CCR5H (*(unsigned char volatile __XDATA *)0xfef5)
|
||||||
|
#define PWMB_CCR5L (*(unsigned char volatile __XDATA *)0xfef6)
|
||||||
|
#define PWMB_CCR6 (*(unsigned int volatile __XDATA *)0xfef7)
|
||||||
|
#define PWMB_CCR6H (*(unsigned char volatile __XDATA *)0xfef7)
|
||||||
|
#define PWMB_CCR6L (*(unsigned char volatile __XDATA *)0xfef8)
|
||||||
|
#define PWMB_CCR7 (*(unsigned int volatile __XDATA *)0xfef9)
|
||||||
|
#define PWMB_CCR7H (*(unsigned char volatile __XDATA *)0xfef9)
|
||||||
|
#define PWMB_CCR7L (*(unsigned char volatile __XDATA *)0xfefa)
|
||||||
|
#define PWMB_CCR8 (*(unsigned int volatile __XDATA *)0xfefb)
|
||||||
|
#define PWMB_CCR8H (*(unsigned char volatile __XDATA *)0xfefb)
|
||||||
|
#define PWMB_CCR8L (*(unsigned char volatile __XDATA *)0xfefc)
|
||||||
|
#define PWMB_BKR (*(unsigned char volatile __XDATA *)0xfefd)
|
||||||
|
#define PWMB_DTR (*(unsigned char volatile __XDATA *)0xfefe)
|
||||||
|
#define PWMB_OISR (*(unsigned char volatile __XDATA *)0xfeff)
|
||||||
|
*/
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FD00H-FDFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define PxINTE 0xfd00
|
||||||
|
#define P0INTE (*(unsigned char volatile __XDATA *)0xfd00)
|
||||||
|
#define P1INTE (*(unsigned char volatile __XDATA *)0xfd01)
|
||||||
|
#define P2INTE (*(unsigned char volatile __XDATA *)0xfd02)
|
||||||
|
#define P3INTE (*(unsigned char volatile __XDATA *)0xfd03)
|
||||||
|
#define P4INTE (*(unsigned char volatile __XDATA *)0xfd04)
|
||||||
|
#define P5INTE (*(unsigned char volatile __XDATA *)0xfd05)
|
||||||
|
#define P6INTE (*(unsigned char volatile __XDATA *)0xfd06)
|
||||||
|
#define P7INTE (*(unsigned char volatile __XDATA *)0xfd07)
|
||||||
|
#define P0INTF (*(unsigned char volatile __XDATA *)0xfd10)
|
||||||
|
#define P1INTF (*(unsigned char volatile __XDATA *)0xfd11)
|
||||||
|
#define P2INTF (*(unsigned char volatile __XDATA *)0xfd12)
|
||||||
|
#define P3INTF (*(unsigned char volatile __XDATA *)0xfd13)
|
||||||
|
#define P4INTF (*(unsigned char volatile __XDATA *)0xfd14)
|
||||||
|
#define P5INTF (*(unsigned char volatile __XDATA *)0xfd15)
|
||||||
|
#define P6INTF (*(unsigned char volatile __XDATA *)0xfd16)
|
||||||
|
#define P7INTF (*(unsigned char volatile __XDATA *)0xfd17)
|
||||||
|
#define PxIM0 0xfd20
|
||||||
|
#define P0IM0 (*(unsigned char volatile __XDATA *)0xfd20)
|
||||||
|
#define P1IM0 (*(unsigned char volatile __XDATA *)0xfd21)
|
||||||
|
#define P2IM0 (*(unsigned char volatile __XDATA *)0xfd22)
|
||||||
|
#define P3IM0 (*(unsigned char volatile __XDATA *)0xfd23)
|
||||||
|
#define P4IM0 (*(unsigned char volatile __XDATA *)0xfd24)
|
||||||
|
#define P5IM0 (*(unsigned char volatile __XDATA *)0xfd25)
|
||||||
|
#define P6IM0 (*(unsigned char volatile __XDATA *)0xfd26)
|
||||||
|
#define P7IM0 (*(unsigned char volatile __XDATA *)0xfd27)
|
||||||
|
#define PxIM1 0xfd30
|
||||||
|
#define P0IM1 (*(unsigned char volatile __XDATA *)0xfd30)
|
||||||
|
#define P1IM1 (*(unsigned char volatile __XDATA *)0xfd31)
|
||||||
|
#define P2IM1 (*(unsigned char volatile __XDATA *)0xfd32)
|
||||||
|
#define P3IM1 (*(unsigned char volatile __XDATA *)0xfd33)
|
||||||
|
#define P4IM1 (*(unsigned char volatile __XDATA *)0xfd34)
|
||||||
|
#define P5IM1 (*(unsigned char volatile __XDATA *)0xfd35)
|
||||||
|
#define P6IM1 (*(unsigned char volatile __XDATA *)0xfd36)
|
||||||
|
#define P7IM1 (*(unsigned char volatile __XDATA *)0xfd37)
|
||||||
|
#define P0WKUE (*(unsigned char volatile __XDATA *)0xfd40)
|
||||||
|
#define P1WKUE (*(unsigned char volatile __XDATA *)0xfd41)
|
||||||
|
#define P2WKUE (*(unsigned char volatile __XDATA *)0xfd42)
|
||||||
|
#define P3WKUE (*(unsigned char volatile __XDATA *)0xfd43)
|
||||||
|
#define P4WKUE (*(unsigned char volatile __XDATA *)0xfd44)
|
||||||
|
#define P5WKUE (*(unsigned char volatile __XDATA *)0xfd45)
|
||||||
|
#define P6WKUE (*(unsigned char volatile __XDATA *)0xfd46)
|
||||||
|
#define P7WKUE (*(unsigned char volatile __XDATA *)0xfd47)
|
||||||
|
#define PIN_IP (*(unsigned char volatile __XDATA *)0xfd60)
|
||||||
|
#define PIN_IPH (*(unsigned char volatile __XDATA *)0xfd61)
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FC00H-FCFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define MD3 (*(unsigned char volatile __XDATA *)0xfcf0)
|
||||||
|
#define MD2 (*(unsigned char volatile __XDATA *)0xfcf1)
|
||||||
|
#define MD1 (*(unsigned char volatile __XDATA *)0xfcf2)
|
||||||
|
#define MD0 (*(unsigned char volatile __XDATA *)0xfcf3)
|
||||||
|
#define MD5 (*(unsigned char volatile __XDATA *)0xfcf4)
|
||||||
|
#define MD4 (*(unsigned char volatile __XDATA *)0xfcf5)
|
||||||
|
#define ARCON (*(unsigned char volatile __XDATA *)0xfcf6)
|
||||||
|
#define OPCON (*(unsigned char volatile __XDATA *)0xfcf7)
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FB00H-FBFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#define COMEN (*(unsigned char volatile __XDATA *)0xfb00)
|
||||||
|
#define SEGENL (*(unsigned char volatile __XDATA *)0xfb01)
|
||||||
|
#define SEGENH (*(unsigned char volatile __XDATA *)0xfb02)
|
||||||
|
#define LEDCTRL (*(unsigned char volatile __XDATA *)0xfb03)
|
||||||
|
#define LEDCKS (*(unsigned char volatile __XDATA *)0xfb04)
|
||||||
|
#define COM0_DA_L (*(unsigned char volatile __XDATA *)0xfb10)
|
||||||
|
#define COM1_DA_L (*(unsigned char volatile __XDATA *)0xfb11)
|
||||||
|
#define COM2_DA_L (*(unsigned char volatile __XDATA *)0xfb12)
|
||||||
|
#define COM3_DA_L (*(unsigned char volatile __XDATA *)0xfb13)
|
||||||
|
#define COM4_DA_L (*(unsigned char volatile __XDATA *)0xfb14)
|
||||||
|
#define COM5_DA_L (*(unsigned char volatile __XDATA *)0xfb15)
|
||||||
|
#define COM6_DA_L (*(unsigned char volatile __XDATA *)0xfb16)
|
||||||
|
#define COM7_DA_L (*(unsigned char volatile __XDATA *)0xfb17)
|
||||||
|
#define COM0_DA_H (*(unsigned char volatile __XDATA *)0xfb18)
|
||||||
|
#define COM1_DA_H (*(unsigned char volatile __XDATA *)0xfb19)
|
||||||
|
#define COM2_DA_H (*(unsigned char volatile __XDATA *)0xfb1a)
|
||||||
|
#define COM3_DA_H (*(unsigned char volatile __XDATA *)0xfb1b)
|
||||||
|
#define COM4_DA_H (*(unsigned char volatile __XDATA *)0xfb1c)
|
||||||
|
#define COM5_DA_H (*(unsigned char volatile __XDATA *)0xfb1d)
|
||||||
|
#define COM6_DA_H (*(unsigned char volatile __XDATA *)0xfb1e)
|
||||||
|
#define COM7_DA_H (*(unsigned char volatile __XDATA *)0xfb1f)
|
||||||
|
#define COM0_DC_L (*(unsigned char volatile __XDATA *)0xfb20)
|
||||||
|
#define COM1_DC_L (*(unsigned char volatile __XDATA *)0xfb21)
|
||||||
|
#define COM2_DC_L (*(unsigned char volatile __XDATA *)0xfb22)
|
||||||
|
#define COM3_DC_L (*(unsigned char volatile __XDATA *)0xfb23)
|
||||||
|
#define COM4_DC_L (*(unsigned char volatile __XDATA *)0xfb24)
|
||||||
|
#define COM5_DC_L (*(unsigned char volatile __XDATA *)0xfb25)
|
||||||
|
#define COM6_DC_L (*(unsigned char volatile __XDATA *)0xfb26)
|
||||||
|
#define COM7_DC_L (*(unsigned char volatile __XDATA *)0xfb27)
|
||||||
|
#define COM0_DC_H (*(unsigned char volatile __XDATA *)0xfb28)
|
||||||
|
#define COM1_DC_H (*(unsigned char volatile __XDATA *)0xfb29)
|
||||||
|
#define COM2_DC_H (*(unsigned char volatile __XDATA *)0xfb2a)
|
||||||
|
#define COM3_DC_H (*(unsigned char volatile __XDATA *)0xfb2b)
|
||||||
|
#define COM4_DC_H (*(unsigned char volatile __XDATA *)0xfb2c)
|
||||||
|
#define COM5_DC_H (*(unsigned char volatile __XDATA *)0xfb2d)
|
||||||
|
#define COM6_DC_H (*(unsigned char volatile __XDATA *)0xfb2e)
|
||||||
|
#define COM7_DC_H (*(unsigned char volatile __XDATA *)0xfb2f)
|
||||||
|
|
||||||
|
#define TSCHEN1 (*(unsigned char volatile __XDATA *)0xfb40)
|
||||||
|
#define TSCHEN2 (*(unsigned char volatile __XDATA *)0xfb41)
|
||||||
|
#define TSCFG1 (*(unsigned char volatile __XDATA *)0xfb42)
|
||||||
|
#define TSCFG2 (*(unsigned char volatile __XDATA *)0xfb43)
|
||||||
|
#define TSWUTC (*(unsigned char volatile __XDATA *)0xfb44)
|
||||||
|
#define TSCTRL (*(unsigned char volatile __XDATA *)0xfb45)
|
||||||
|
#define TSSTA1 (*(unsigned char volatile __XDATA *)0xfb46)
|
||||||
|
#define TSSTA2 (*(unsigned char volatile __XDATA *)0xfb47)
|
||||||
|
#define TSRT (*(unsigned char volatile __XDATA *)0xfb48)
|
||||||
|
#define TSDAT (*(unsigned int volatile __XDATA *)0xfb49)
|
||||||
|
#define TSDATH (*(unsigned char volatile __XDATA *)0xfb49)
|
||||||
|
#define TSDATL (*(unsigned char volatile __XDATA *)0xfb4A)
|
||||||
|
#define TSTH00 (*(unsigned int volatile __XDATA *)0xfb50)
|
||||||
|
#define TSTH00H (*(unsigned char volatile __XDATA *)0xfb50)
|
||||||
|
#define TSTH00L (*(unsigned char volatile __XDATA *)0xfb51)
|
||||||
|
#define TSTH01 (*(unsigned int volatile __XDATA *)0xfb52)
|
||||||
|
#define TSTH01H (*(unsigned char volatile __XDATA *)0xfb52)
|
||||||
|
#define TSTH01L (*(unsigned char volatile __XDATA *)0xfb53)
|
||||||
|
#define TSTH02 (*(unsigned int volatile __XDATA *)0xfb54)
|
||||||
|
#define TSTH02H (*(unsigned char volatile __XDATA *)0xfb54)
|
||||||
|
#define TSTH02L (*(unsigned char volatile __XDATA *)0xfb55)
|
||||||
|
#define TSTH03 (*(unsigned int volatile __XDATA *)0xfb56)
|
||||||
|
#define TSTH03H (*(unsigned char volatile __XDATA *)0xfb56)
|
||||||
|
#define TSTH03L (*(unsigned char volatile __XDATA *)0xfb57)
|
||||||
|
#define TSTH04 (*(unsigned int volatile __XDATA *)0xfb58)
|
||||||
|
#define TSTH04H (*(unsigned char volatile __XDATA *)0xfb58)
|
||||||
|
#define TSTH04L (*(unsigned char volatile __XDATA *)0xfb59)
|
||||||
|
#define TSTH05 (*(unsigned int volatile __XDATA *)0xfb5a)
|
||||||
|
#define TSTH05H (*(unsigned char volatile __XDATA *)0xfb5a)
|
||||||
|
#define TSTH05L (*(unsigned char volatile __XDATA *)0xfb5b)
|
||||||
|
#define TSTH06 (*(unsigned int volatile __XDATA *)0xfb5c)
|
||||||
|
#define TSTH06H (*(unsigned char volatile __XDATA *)0xfb5c)
|
||||||
|
#define TSTH06L (*(unsigned char volatile __XDATA *)0xfb5d)
|
||||||
|
#define TSTH07 (*(unsigned int volatile __XDATA *)0xfb5e)
|
||||||
|
#define TSTH07H (*(unsigned char volatile __XDATA *)0xfb5e)
|
||||||
|
#define TSTH07L (*(unsigned char volatile __XDATA *)0xfb5f)
|
||||||
|
#define TSTH08 (*(unsigned int volatile __XDATA *)0xfb60)
|
||||||
|
#define TSTH08H (*(unsigned char volatile __XDATA *)0xfb60)
|
||||||
|
#define TSTH08L (*(unsigned char volatile __XDATA *)0xfb61)
|
||||||
|
#define TSTH09 (*(unsigned int volatile __XDATA *)0xfb62)
|
||||||
|
#define TSTH09H (*(unsigned char volatile __XDATA *)0xfb62)
|
||||||
|
#define TSTH09L (*(unsigned char volatile __XDATA *)0xfb63)
|
||||||
|
#define TSTH10 (*(unsigned int volatile __XDATA *)0xfb64)
|
||||||
|
#define TSTH10H (*(unsigned char volatile __XDATA *)0xfb64)
|
||||||
|
#define TSTH10L (*(unsigned char volatile __XDATA *)0xfb65)
|
||||||
|
#define TSTH11 (*(unsigned int volatile __XDATA *)0xfb66)
|
||||||
|
#define TSTH11H (*(unsigned char volatile __XDATA *)0xfb66)
|
||||||
|
#define TSTH11L (*(unsigned char volatile __XDATA *)0xfb67)
|
||||||
|
#define TSTH12 (*(unsigned int volatile __XDATA *)0xfb68)
|
||||||
|
#define TSTH12H (*(unsigned char volatile __XDATA *)0xfb68)
|
||||||
|
#define TSTH12L (*(unsigned char volatile __XDATA *)0xfb69)
|
||||||
|
#define TSTH13 (*(unsigned int volatile __XDATA *)0xfb6a)
|
||||||
|
#define TSTH13H (*(unsigned char volatile __XDATA *)0xfb6a)
|
||||||
|
#define TSTH13L (*(unsigned char volatile __XDATA *)0xfb6b)
|
||||||
|
#define TSTH14 (*(unsigned int volatile __XDATA *)0xfb6c)
|
||||||
|
#define TSTH14H (*(unsigned char volatile __XDATA *)0xfb6c)
|
||||||
|
#define TSTH14L (*(unsigned char volatile __XDATA *)0xfb6d)
|
||||||
|
#define TSTH15 (*(unsigned int volatile __XDATA *)0xfb6e)
|
||||||
|
#define TSTH15H (*(unsigned char volatile __XDATA *)0xfb6e)
|
||||||
|
#define TSTH15L (*(unsigned char volatile __XDATA *)0xfb6f)
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
//FA00H-FAFFH
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#endif
|
||||||
28
include/fw_sys.h
Normal file
28
include/fw_sys.h
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
#ifndef ___FW_SYS_H___
|
||||||
|
#define ___FW_SYS_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
|
||||||
|
#define SYS_SetFOSC(__IRCBAND__, __VRTRIM__, __IRTRIM__, __LIRTRIM__) do { \
|
||||||
|
IRCBAND = ((__IRCBAND__) & 0x03); \
|
||||||
|
VRTRIM = (__VRTRIM__); \
|
||||||
|
IRTRIM = (__IRTRIM__); \
|
||||||
|
LIRTRIM = ((__LIRTRIM__) & 0x03); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* STC8H Clock:
|
||||||
|
* MCKSEL ||===> MCLKODIV ==> MCLKO_S => P1.6/P5.4
|
||||||
|
* 00 Internal IRC | ||
|
||||||
|
* 01 External OSC |==> CLKDIV ==> SYSCLK
|
||||||
|
* 10 External 32KHz |
|
||||||
|
* 11 Internal 32KHz |
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef SYS_Init(void);
|
||||||
|
void SYS_Delay(uint16_t t);
|
||||||
|
void SYS_DelayUs(uint16_t t);
|
||||||
|
void SYS_SetSysClkDiv(uint8_t div);
|
||||||
|
uint32_t SYS_GetSysClk(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
117
include/fw_tim.h
Normal file
117
include/fw_tim.h
Normal file
@ -0,0 +1,117 @@
|
|||||||
|
#ifndef ___FW_TIM_H___
|
||||||
|
#define ___FW_TIM_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
#include "fw_exti.h"
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
TIM_TimerMode_16BitAuto = 0x00, // 16-bit auto-reload from [TH0,TL0](Timer0), [TH1,TL1](Timer1)
|
||||||
|
TIM_TimerMode_16Bit = 0x01, // 16-bit no-auto-reload
|
||||||
|
TIM_TimerMode_8BitAuto = 0x02, // 8-bit auto-reload from TH0(Timer0), TH1(Timer1)
|
||||||
|
TIM_TimerMode_16BitAutoNoInt = 0x03 // Uninterruptable 16-bit auto-reload, Timer0 only
|
||||||
|
} TIM_TimerMode_t;
|
||||||
|
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* Timer 0
|
||||||
|
*/
|
||||||
|
#define TIM_Timer0_SetRunState(__STATE__) SBIT_ASSIGN(TR0, __STATE__)
|
||||||
|
#define TIM_Timer0_SetGateState(__STATE__) SFR_ASSIGN(TMOD, 3, __STATE__)
|
||||||
|
#define TIM_Timer0_SetFuncCounter SFR_SET(TMOD, 2)
|
||||||
|
#define TIM_Timer0_SetFuncTimer SFR_RESET(TMOD, 2)
|
||||||
|
// ON:FOSC, OFF:FOSC/12
|
||||||
|
#define TIM_Timer0_Set1TMode(__STATE__) SFR_ASSIGN(AUXR, 7, __STATE__)
|
||||||
|
// Enable output on P3.5, when counter overflow, P3.5 switch voltage level
|
||||||
|
#define TIM_Timer0_SetOutput(__STATE__) SFR_ASSIGN(INTCLKO, 0, __STATE__)
|
||||||
|
#define TIM_Timer0_SetMode(__TIM_TIMER_MODE__) (TMOD = TMOD & ~(0x03 << 0) | ((__TIM_TIMER_MODE__) << 0))
|
||||||
|
#define TIM_Timer0_SetInitValue(__TH__, __TL__) do{ TH0 = (__TH__); TL0 = (__TL__); }while(0)
|
||||||
|
|
||||||
|
void TIM_Timer0_Config(
|
||||||
|
HAL_State_t freq1t,
|
||||||
|
TIM_TimerMode_t mode,
|
||||||
|
uint16_t frequency,
|
||||||
|
HAL_State_t intState,
|
||||||
|
EXTI_IntPriority_t intPriority);
|
||||||
|
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* Timer 1
|
||||||
|
*/
|
||||||
|
#define TIM_Timer1_SetRunState(__STATE__) SBIT_ASSIGN(TR1, __STATE__)
|
||||||
|
#define TIM_Timer1_SetGateState(__STATE__) SFR_ASSIGN(TMOD, 7, __STATE__)
|
||||||
|
#define TIM_Timer1_FuncCounter SFR_SET(TMOD, 6)
|
||||||
|
#define TIM_Timer1_FuncTimer SFR_RESET(TMOD, 6)
|
||||||
|
// ON:FOSC, OFF:FOSC/12
|
||||||
|
#define TIM_Timer1_Set1TMode(__STATE__) SFR_ASSIGN(AUXR, 6, __STATE__)
|
||||||
|
// Enable output on P3.4, when counter overflow, P3.4 switch voltage level
|
||||||
|
#define TIM_Timer1_SetOutput(__STATE__) SFR_ASSIGN(INTCLKO, 1, __STATE__)
|
||||||
|
#define TIM_Timer1_SetMode(__TIM_TIMER_MODE__) (TMOD = TMOD & ~(0x03 << 4) | ((__TIM_TIMER_MODE__) << 4))
|
||||||
|
#define TIM_Timer1_SetInitValue(__TH__, __TL__) do{ TH1 = (__TH__); TL1 = (__TL__); }while(0)
|
||||||
|
|
||||||
|
void TIM_Timer1_Config(
|
||||||
|
HAL_State_t freq1t,
|
||||||
|
TIM_TimerMode_t mode,
|
||||||
|
uint16_t frequency,
|
||||||
|
HAL_State_t intState,
|
||||||
|
EXTI_IntPriority_t intPriority);
|
||||||
|
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* Timer 2,3,4 (STC8H3K only)
|
||||||
|
*
|
||||||
|
* ||=> 12T Mode => |
|
||||||
|
* | | |Counter| |=> TxIF Interrupt
|
||||||
|
* SYSCLK => TMxPS => | |=> |Timer | => TxR => TxH|TxL =>|
|
||||||
|
* | | |=> TxCLKO => Output
|
||||||
|
* ||=> 1T Mode => |
|
||||||
|
*/
|
||||||
|
#define TIM_Timer2_SetRunState(__STATE__) SFR_ASSIGN(AUXR, 4, __STATE__)
|
||||||
|
#define TIM_Timer2_FuncCounter SFR_SET(AUXR, 3)
|
||||||
|
#define TIM_Timer2_FuncTimer SFR_RESET(AUXR, 3)
|
||||||
|
// ON:FOSC, OFF:FOSC/12
|
||||||
|
#define TIM_Timer2_Set1TMode(__STATE__) SFR_ASSIGN(AUXR, 2, __STATE__)
|
||||||
|
// Enable output on P1.3, when counter overflow, P1.3 switch voltage level
|
||||||
|
#define TIM_Timer2_SetOutput(__STATE__) SFR_ASSIGN(INTCLKO, 2, __STATE__)
|
||||||
|
#define TIM_Timer2_SetInitValue(__TH__, __TL__) do{ T2H = (__TH__); T2L = (__TL__); }while(0)
|
||||||
|
// Timer2 Prescaler: [0, 255]
|
||||||
|
#define TIM_Timer2_SetPreScaler(__PRE__) do{P_SW2 = 0x80; TM2PS = (__PRE__); P_SW2 = 0x00;}while(0)
|
||||||
|
|
||||||
|
void TIM_Timer2_Config(HAL_State_t freq1t, uint8_t prescaler, uint16_t frequency, HAL_State_t intState);
|
||||||
|
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* Timer 3
|
||||||
|
*/
|
||||||
|
#define TIM_Timer3_SetRunState(__STATE__) SFR_ASSIGN(T4T3M, 3, __STATE__)
|
||||||
|
#define TIM_Timer3_FuncCounter SFR_SET(T4T3M, 2)
|
||||||
|
#define TIM_Timer3_FuncTimer SFR_RESET(T4T3M, 2)
|
||||||
|
// ON:FOSC, OFF:FOSC/12
|
||||||
|
#define TIM_Timer3_Set1TMode(__STATE__) SFR_ASSIGN(T4T3M, 1, __STATE__)
|
||||||
|
// Enable output on P0.4
|
||||||
|
#define TIM_Timer3_SetOutput(__STATE__) SFR_ASSIGN(T4T3M, 0, __STATE__)
|
||||||
|
#define TIM_Timer3_SetInitValue(__TH__, __TL__) do{ T3H = (__TH__); T3L = (__TL__); }while(0)
|
||||||
|
// Timer3 Prescaler: [0, 255]
|
||||||
|
#define TIM_Timer3_SetPreScaler(__PRE__) do{P_SW2 = 0x80; TM3PS = (__PRE__); P_SW2 = 0x00;}while(0)
|
||||||
|
|
||||||
|
void TIM_Timer3_Config(HAL_State_t freq1t, uint8_t prescaler, uint16_t frequency, HAL_State_t intState);
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* Timer 4
|
||||||
|
*/
|
||||||
|
#define TIM_Timer4_SetRunState(__STATE__) SFR_ASSIGN(T4T3M, 7, __STATE__)
|
||||||
|
#define TIM_Timer4_FuncCounter SFR_SET(T4T3M, 6)
|
||||||
|
#define TIM_Timer4_FuncTimer SFR_RESET(T4T3M, 6)
|
||||||
|
// ON:FOSC, OFF:FOSC/12
|
||||||
|
#define TIM_Timer4_Set1TMode(__STATE__) SFR_ASSIGN(T4T3M, 5, __STATE__)
|
||||||
|
// Enable output on P0.7
|
||||||
|
#define TIM_Timer4_SetOutput(__STATE__) SFR_ASSIGN(T4T3M, 4, __STATE__)
|
||||||
|
#define TIM_Timer4_SetInitValue(__TH__, __TL__) do{ T4H = (__TH__); T4L = (__TL__); }while(0)
|
||||||
|
// Timer4 Prescaler: [0, 255]
|
||||||
|
#define TIM_Timer4_SetPreScaler(__PRE__) do{P_SW2 = 0x80; TM4PS = (__PRE__); P_SW2 = 0x00;}while(0)
|
||||||
|
|
||||||
|
void TIM_Timer4_Config(HAL_State_t freq1t, uint8_t prescaler, uint16_t frequency, HAL_State_t intState);
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
110
include/fw_types.h
Normal file
110
include/fw_types.h
Normal file
@ -0,0 +1,110 @@
|
|||||||
|
#ifndef ___FW_TYPES_H___
|
||||||
|
#define ___FW_TYPES_H___
|
||||||
|
|
||||||
|
typedef unsigned char uint8_t;
|
||||||
|
typedef unsigned short uint16_t;
|
||||||
|
typedef unsigned long uint32_t;
|
||||||
|
typedef uint32_t uint64_t[2];
|
||||||
|
|
||||||
|
typedef signed char int8_t;
|
||||||
|
typedef short int16_t;
|
||||||
|
typedef long int32_t;
|
||||||
|
typedef int32_t int64_t[2];
|
||||||
|
|
||||||
|
|
||||||
|
#define B00000000 0x00
|
||||||
|
#define B00000001 0x01
|
||||||
|
#define B00000010 0x02
|
||||||
|
#define B00000011 0x03
|
||||||
|
#define B00000100 0x04
|
||||||
|
#define B00000110 0x06
|
||||||
|
#define B00000111 0x07
|
||||||
|
#define B00001000 0x08
|
||||||
|
#define B00001100 0x0C
|
||||||
|
#define B00001110 0x0E
|
||||||
|
#define B00001111 0x0F
|
||||||
|
#define B00010000 0x10
|
||||||
|
#define B00011000 0x18
|
||||||
|
#define B00011100 0x1C
|
||||||
|
#define B00011110 0x1E
|
||||||
|
#define B00011111 0x1F
|
||||||
|
#define B00100000 0x20
|
||||||
|
#define B00110000 0x30
|
||||||
|
#define B00111000 0x38
|
||||||
|
#define B00111100 0x3C
|
||||||
|
#define B00111110 0x3E
|
||||||
|
#define B00111111 0x3F
|
||||||
|
#define B01000000 0x40
|
||||||
|
#define B01100000 0x60
|
||||||
|
#define B01110000 0x70
|
||||||
|
#define B01111000 0x78
|
||||||
|
#define B01111100 0x7C
|
||||||
|
#define B01111110 0x7E
|
||||||
|
#define B01111111 0x7F
|
||||||
|
#define B10000000 0x80
|
||||||
|
#define B11000000 0xC0
|
||||||
|
#define B11100000 0xE0
|
||||||
|
#define B11110000 0xF0
|
||||||
|
#define B11111000 0xF8
|
||||||
|
#define B11111100 0xFC
|
||||||
|
#define B11111110 0xFE
|
||||||
|
#define B11111111 0xFF
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_State_OFF = 0x00,
|
||||||
|
HAL_State_ON = 0x01,
|
||||||
|
} HAL_State_t;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_OK = 0x00U,
|
||||||
|
HAL_ERROR = 0x01U,
|
||||||
|
HAL_BUSY = 0x02U,
|
||||||
|
HAL_TIMEOUT = 0x03U
|
||||||
|
} HAL_StatusTypeDef;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RESET = 0x0,
|
||||||
|
SET = !RESET
|
||||||
|
} FlagStatus;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* sbit operations
|
||||||
|
*/
|
||||||
|
#define SBIT_SET(__BIT__) ((__BIT__) = SET)
|
||||||
|
#define SBIT_RESET(__BIT__) ((__BIT__) = RESET)
|
||||||
|
#define SBIT_ASSIGN(__BIT__, __VAL__) ((__BIT__) = (__VAL__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* sfr bit operations
|
||||||
|
*/
|
||||||
|
#define SFR_SET(__SFR__, __POS__) ((__SFR__) |= (0x01 << (__POS__)))
|
||||||
|
#define SFR_RESET(__SFR__, __POS__) ((__SFR__) &= ~(0x01 << (__POS__)))
|
||||||
|
#define SFR_ASSIGN(__SFR__, __POS__, __VAL__) ((__SFR__) = (__SFR__) & ~(0x01 << (__POS__)) | ((__VAL__) << (__POS__)))
|
||||||
|
// For dual sfr bit (one for each) operation
|
||||||
|
#define SFR_DUAL_SET(__SFR0__, __SFR1__, __POS__, __VAL__) do { \
|
||||||
|
(__SFR0__) = (__SFR0__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x01)? (0x01 << (__POS__)) : 0x00); \
|
||||||
|
(__SFR1__) = (__SFR1__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x02)? (0x01 << (__POS__)) : 0x00); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* xdata sfr operations
|
||||||
|
*/
|
||||||
|
#define SFRX_SET(__SFR__, __POS__) do {P_SW2 = 0x80; (__SFR__) |= (0x01 << (__POS__)); P_SW2 = 0x00;} while(0)
|
||||||
|
#define SFRX_RESET(__SFR__, __POS__) do {P_SW2 = 0x80; (__SFR__) &= ~(0x01 << (__POS__)); P_SW2 = 0x00;} while(0)
|
||||||
|
#define SFRX_ASSIGN(__SFR__, __POS__, __VAL__) do { \
|
||||||
|
P_SW2 = 0x80; \
|
||||||
|
(__SFR__) = (__SFR__) & ~(0x01 << (__POS__)) | ((__VAL__) << (__POS__)); \
|
||||||
|
P_SW2 = 0x00; \
|
||||||
|
} while(0)
|
||||||
|
// For dual xdata sfr bit (one for each) operation
|
||||||
|
#define SFRX_DUAL_SET(__SFR0__, __SFR1__, __POS__, __VAL__) do { \
|
||||||
|
P_SW2 = 0x80; \
|
||||||
|
(__SFR0__) = (__SFR0__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x01)? (0x01 << (__POS__)) : 0x00); \
|
||||||
|
(__SFR1__) = (__SFR1__) & ~(0x01 << (__POS__)) | (((__VAL__) & 0x02)? (0x01 << (__POS__)) : 0x00); \
|
||||||
|
P_SW2 = 0x00; \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
#endif
|
||||||
85
include/fw_uart.h
Normal file
85
include/fw_uart.h
Normal file
@ -0,0 +1,85 @@
|
|||||||
|
#ifndef ___FW_UART_H___
|
||||||
|
#define ___FW_UART_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
#include "fw_exti.h"
|
||||||
|
|
||||||
|
#define UART_RX_BUFF_SIZE 0x20
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* UART1
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
UART1_BaudSource_Timer1 = 0x00,
|
||||||
|
UART1_BaudSource_Timer2 = 0x01,
|
||||||
|
} UART1_BaudSource_t;
|
||||||
|
|
||||||
|
#define UART1_SetRxState(__STATE__) SBIT_ASSIGN(REN, __STATE__)
|
||||||
|
#define UART1_ClearTxInterrupt SBIT_RESET(TI)
|
||||||
|
#define UART1_ClearRxInterrupt SBIT_RESET(RI)
|
||||||
|
#define UART1_WriteBuffer(__DATA__) (SBUF = (__DATA__))
|
||||||
|
#define UART1_SetFrameErrDetect(__STATE__) SFR_ASSIGN(PCON, 6, __STATE__)
|
||||||
|
#define UART1_SetBaudSource(__BAUD_SRC__) SFR_ASSIGN(AUXR, 0, __BAUD_SRC__)
|
||||||
|
/**
|
||||||
|
* Mode0: Synchronous shift serial mode, baudrate is fixed, provided by SYSCLK
|
||||||
|
* Baud = (UART_M0x6 = 0)? (SYSCLK/12) : (SYSCLK/2)
|
||||||
|
*/
|
||||||
|
#define UART1_ConfigMode0FixedSyncSerial(__STATE__) do{ SM0=0; SM1=0; SFR_ASSIGN(AUXR, 5, __STATE__);}while(0)
|
||||||
|
#define UART1_SetMode0Baudx6(__STATE__) SFR_ASSIGN(AUXR, 5, __STATE__)
|
||||||
|
/**
|
||||||
|
* Mode2: 9-bit UART mode, baudrate is fixed, provided by SYSCLK
|
||||||
|
* Baud = (SMOD = 0)? (SYSCLK/64) : (SYSCLK/32)
|
||||||
|
*/
|
||||||
|
#define UART1_ConfigMode2Fixed9bitUart(__STATE__) do{ SM0=1; SM1=0; SFR_ASSIGN(PCON, 7, __STATE__);}while(0)
|
||||||
|
#define UART1_SetTimer1Mode2Baudx2(__STATE__) SFR_ASSIGN(PCON, 7, __STATE__)
|
||||||
|
/**
|
||||||
|
* Mode1: 8-bit UART, dynamic baud-rate, provided by Timer1 or Timer2
|
||||||
|
*/
|
||||||
|
void UART1_ConfigMode1Dyn8bitUart(
|
||||||
|
UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt);
|
||||||
|
/**
|
||||||
|
* Mode3: 9-bit UART, dynamic baud-rate, provided by Timer1 or Timer2
|
||||||
|
*/
|
||||||
|
void UART1_ConfigMode3Dyn9bitUart(
|
||||||
|
UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt);
|
||||||
|
|
||||||
|
void UART1_InterruptHandler(void);
|
||||||
|
|
||||||
|
void UART1_IntTxChar(char dat);
|
||||||
|
void UART1_IntTxHex(uint8_t hex);
|
||||||
|
void UART1_IntTxString(uint8_t *str);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* FIXME: If place this in first with following TXString(), sending may not work. didn't find the reason
|
||||||
|
*/
|
||||||
|
void UART1_TxChar(char dat);
|
||||||
|
void UART1_TxHex(uint8_t hex);
|
||||||
|
void UART1_TxString(uint8_t *str);
|
||||||
|
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* UART2
|
||||||
|
*/
|
||||||
|
#define UART2_SetRxState(__STATE__) SFR_ASSIGN(S2CON, 4, __STATE__)
|
||||||
|
#define UART2_ClearTxInterrupt SFR_RESET(S2CON, 1)
|
||||||
|
#define UART2_ClearRxInterrupt SFR_RESET(S2CON, 0)
|
||||||
|
#define UART2_WriteBuffer(__DATA__) (S2BUF = (__DATA__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Mode0: 8-bit UART, dynamic baud-rate, provided by Timer2
|
||||||
|
*/
|
||||||
|
void UART2_ConfigMode0Dyn8bitUart(
|
||||||
|
HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt);
|
||||||
|
/**
|
||||||
|
* Mode1: 9-bit UART, dynamic baud-rate, provided by Timer2
|
||||||
|
*/
|
||||||
|
void UART2_ConfigMode1Dyn9bitUart(
|
||||||
|
HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt);
|
||||||
|
|
||||||
|
void UART2_TxChar(char dat);
|
||||||
|
void UART2_TxHex(uint8_t hex);
|
||||||
|
void UART2_TxString(uint8_t *str);
|
||||||
|
|
||||||
|
#endif
|
||||||
16
include/fw_util.h
Normal file
16
include/fw_util.h
Normal file
@ -0,0 +1,16 @@
|
|||||||
|
#ifndef ___FW_UTIL_H___
|
||||||
|
#define ___FW_UTIL_H___
|
||||||
|
|
||||||
|
#include "fw_conf.h"
|
||||||
|
#include "fw_types.h"
|
||||||
|
|
||||||
|
void UTIL_Uart1_24M_9600_Init(void);
|
||||||
|
void UTIL_Uart1_24M_115200_Init(void);
|
||||||
|
void UTIL_Uart1_33M1776_9600_Init(void);
|
||||||
|
void UTIL_Uart1_33M1776_115200_Init(void);
|
||||||
|
void UTIL_Uart1_35M_9600_Init(void);
|
||||||
|
void UTIL_Uart1_36M864_9600_Init(void);
|
||||||
|
void UTIL_Uart1_36M864_115200_Init(void);
|
||||||
|
void UTIL_ItrimScan(uint8_t ircband, uint8_t *str);
|
||||||
|
|
||||||
|
#endif
|
||||||
8
library.json
Normal file
8
library.json
Normal file
@ -0,0 +1,8 @@
|
|||||||
|
{
|
||||||
|
"name": "FwLib_STC8",
|
||||||
|
"version": "1.0",
|
||||||
|
"build": {
|
||||||
|
"srcDir": "src",
|
||||||
|
"includeDir": "include"
|
||||||
|
}
|
||||||
|
}
|
||||||
2
src/fw_exti.c
Normal file
2
src/fw_exti.c
Normal file
@ -0,0 +1,2 @@
|
|||||||
|
#include "fw_exti.h"
|
||||||
|
|
||||||
6
src/fw_gpio.c
Normal file
6
src/fw_gpio.c
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
#include "fw_gpio.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
12
src/fw_mem.c
Normal file
12
src/fw_mem.c
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
#include "fw_mem.h"
|
||||||
|
|
||||||
|
void MEM_SelectWorkRegGroup(MEM_WorkRegGroup_t WorkRegGroup)
|
||||||
|
{
|
||||||
|
RS0 = WorkRegGroup & B00000001;
|
||||||
|
RS1 = (WorkRegGroup >> 1) & B00000001;
|
||||||
|
}
|
||||||
|
|
||||||
|
void MEM_SetOnchipExtRAM(HAL_State_t HAL_State)
|
||||||
|
{
|
||||||
|
AUXR = AUXR & ~B00000010 | (HAL_State << 1);
|
||||||
|
}
|
||||||
79
src/fw_rcc.c
Normal file
79
src/fw_rcc.c
Normal file
@ -0,0 +1,79 @@
|
|||||||
|
#include "fw_rcc.h"
|
||||||
|
|
||||||
|
void RCC_SetSYSCLKSource(RCC_SYSCLKSource_t SYSCLKSource)
|
||||||
|
{
|
||||||
|
P_SW2 = 0x80;
|
||||||
|
if (SYSCLKSource == RCC_SYSCLKSource_HSI)
|
||||||
|
{
|
||||||
|
// Enable internal high speed rc osc
|
||||||
|
HIRCCR |= B10000000;
|
||||||
|
while(!(HIRCCR & B00000001));
|
||||||
|
}
|
||||||
|
else if (SYSCLKSource == RCC_SYSCLKSource_HSE)
|
||||||
|
{
|
||||||
|
// Enable external high speed osc
|
||||||
|
XOSCCR |= B10000000;
|
||||||
|
while(!(XOSCCR & B00000001));
|
||||||
|
}
|
||||||
|
else if (SYSCLKSource == RCC_SYSCLKSource_LSE)
|
||||||
|
{
|
||||||
|
// Enable external 32khz osc
|
||||||
|
X32KCR |= B10000000;
|
||||||
|
while(!(X32KCR & B00000001));
|
||||||
|
}
|
||||||
|
else if (SYSCLKSource == RCC_SYSCLKSource_LSI)
|
||||||
|
{
|
||||||
|
// Enable internal 32khz rc osc
|
||||||
|
IRC32KCR |= B10000000;
|
||||||
|
while(!(IRC32KCR & B00000001));
|
||||||
|
}
|
||||||
|
CKSEL = CKSEL & ~(B00000011) | SYSCLKSource;
|
||||||
|
P_SW2 = 0x00;
|
||||||
|
}
|
||||||
|
|
||||||
|
void RCC_SetCLKDivider(uint8_t divider)
|
||||||
|
{
|
||||||
|
P_SW2 = 0x80;
|
||||||
|
CLKDIV = divider;
|
||||||
|
P_SW2 = 0x00;
|
||||||
|
}
|
||||||
|
|
||||||
|
void RCC_SetIRC(RCC_IRCBand_t IRCBand, uint8_t IRTrim, RCC_LIRTrim_t LIRTrim)
|
||||||
|
{
|
||||||
|
IRCBAND = IRCBAND & ~(B00000001) | IRCBand;
|
||||||
|
IRTRIM = IRTrim;
|
||||||
|
LIRTRIM = LIRTRIM & ~(B00000011) | LIRTrim;
|
||||||
|
}
|
||||||
|
|
||||||
|
void RCC_SoftwareReset(RCC_SoftwareReset_t SoftwareReset)
|
||||||
|
{
|
||||||
|
/* IAP_CONTR = IAP_CONTR & ~(B0011 << 5) | (((SoftwareReset << 1) | B0001) << 5);*/
|
||||||
|
IAP_CONTR |= ((SoftwareReset << 1) | B00000001) << 5;
|
||||||
|
}
|
||||||
|
|
||||||
|
void RCC_ConfigLowVoltReset(
|
||||||
|
HAL_State_t HAL_State,
|
||||||
|
RCC_LowVoltResetPinAF_t LowVoltResetPinAF,
|
||||||
|
RCC_LowVoltDetectVolt_t LowVoltDetectVolt)
|
||||||
|
{
|
||||||
|
RSTCFG = RSTCFG
|
||||||
|
& ~(B01000000 | B00010000 | B00000011)
|
||||||
|
| ((HAL_State << 6)|(LowVoltResetPinAF << 4)|(LowVoltDetectVolt));
|
||||||
|
}
|
||||||
|
|
||||||
|
void RCC_SetPowerDownWakeupTimer(HAL_State_t HAL_State, uint16_t countdown)
|
||||||
|
{
|
||||||
|
WKTCH = WKTCH & ~B10000000 | (HAL_State << 7);
|
||||||
|
WKTCH = WKTCH & ~B01111111 | ((countdown >> 8) & B01111111);
|
||||||
|
WKTCL = countdown & 0xFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
void RCC_SetPowerDownMode(HAL_State_t HAL_State)
|
||||||
|
{
|
||||||
|
PCON |= (HAL_State << 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void RCC_SetIdleMode(HAL_State_t HAL_State)
|
||||||
|
{
|
||||||
|
PCON |= (HAL_State);
|
||||||
|
}
|
||||||
48
src/fw_sys.c
Normal file
48
src/fw_sys.c
Normal file
@ -0,0 +1,48 @@
|
|||||||
|
#include "fw_sys.h"
|
||||||
|
|
||||||
|
static const uint16_t ticks_ms = (__CONF_FOSC / (float)1000 / 13 - 46);
|
||||||
|
static const uint8_t ticks_us = (__CONF_FOSC / (float)12100000UL);
|
||||||
|
static uint8_t clkdiv = 0x1;
|
||||||
|
|
||||||
|
HAL_StatusTypeDef SYS_Init(void)
|
||||||
|
{
|
||||||
|
SYS_SetSysClkDiv(0);
|
||||||
|
SYS_SetFOSC(__CONF_IRCBAND, __CONF_VRTRIM, __CONF_IRTRIM, __CONF_LIRTRIM);
|
||||||
|
// Wait a while till sysclk stable, or it may block the main process
|
||||||
|
uint16_t i = ticks_ms;
|
||||||
|
while (--i);
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
void SYS_Delay(uint16_t t)
|
||||||
|
{
|
||||||
|
uint16_t i;
|
||||||
|
do
|
||||||
|
{
|
||||||
|
i = ticks_ms;
|
||||||
|
while (--i);
|
||||||
|
} while (--t);
|
||||||
|
}
|
||||||
|
|
||||||
|
void SYS_DelayUs(uint16_t t)
|
||||||
|
{
|
||||||
|
uint8_t i;
|
||||||
|
do
|
||||||
|
{
|
||||||
|
i = ticks_us;
|
||||||
|
while (--i);
|
||||||
|
} while (--t);
|
||||||
|
}
|
||||||
|
|
||||||
|
void SYS_SetSysClkDiv(uint8_t div)
|
||||||
|
{
|
||||||
|
P_SW2 = 0x80;
|
||||||
|
CLKDIV = div;
|
||||||
|
P_SW2 = 0x00;
|
||||||
|
clkdiv = (div == 0)? 1 : div;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t SYS_GetSysClk(void)
|
||||||
|
{
|
||||||
|
return ((uint32_t)__CONF_FOSC) / clkdiv;
|
||||||
|
}
|
||||||
122
src/fw_tim.c
Normal file
122
src/fw_tim.c
Normal file
@ -0,0 +1,122 @@
|
|||||||
|
#include "fw_tim.h"
|
||||||
|
#include "fw_exti.h"
|
||||||
|
#include "fw_sys.h"
|
||||||
|
#include "fw_util.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Calculate the initial value of timer counter
|
||||||
|
* - If the frequency is too high, it will return the value of `limit`, so the timer
|
||||||
|
* will run in the highest frequency
|
||||||
|
* - If the frequency is too low, it will return 0, so the timer will run in the
|
||||||
|
* lowest possible frequency
|
||||||
|
*/
|
||||||
|
int16_t _TIM_InitValueCalculate(uint16_t frequency, HAL_State_t freq1t, uint16_t limit)
|
||||||
|
{
|
||||||
|
uint32_t value = SYS_GetSysClk();
|
||||||
|
if (!freq1t)
|
||||||
|
value = value / 12;
|
||||||
|
value = value / frequency;
|
||||||
|
if (value > limit)
|
||||||
|
return 0;
|
||||||
|
else
|
||||||
|
return limit - value;
|
||||||
|
}
|
||||||
|
|
||||||
|
void TIM_Timer0_Config(
|
||||||
|
HAL_State_t freq1t,
|
||||||
|
TIM_TimerMode_t mode,
|
||||||
|
uint16_t frequency,
|
||||||
|
HAL_State_t intState,
|
||||||
|
EXTI_IntPriority_t intPriority)
|
||||||
|
{
|
||||||
|
uint16_t init;
|
||||||
|
TIM_Timer0_Set1TMode(freq1t);
|
||||||
|
TIM_Timer0_SetMode(mode);
|
||||||
|
if (mode == TIM_TimerMode_8BitAuto)
|
||||||
|
{
|
||||||
|
init = _TIM_InitValueCalculate(frequency, freq1t, 0xFF);
|
||||||
|
TIM_Timer0_SetInitValue(init & 0xFF, init & 0xFF);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
init = _TIM_InitValueCalculate(frequency, freq1t, 0xFFFF);
|
||||||
|
TIM_Timer0_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
}
|
||||||
|
EXTI_Timer0_SetIntState(intState);
|
||||||
|
EXTI_Timer0_SetIntPriority(intPriority);
|
||||||
|
}
|
||||||
|
|
||||||
|
void TIM_Timer1_Config(
|
||||||
|
HAL_State_t freq1t,
|
||||||
|
TIM_TimerMode_t mode,
|
||||||
|
uint16_t frequency,
|
||||||
|
HAL_State_t intState,
|
||||||
|
EXTI_IntPriority_t intPriority)
|
||||||
|
{
|
||||||
|
uint16_t init;
|
||||||
|
TIM_Timer1_Set1TMode(freq1t);
|
||||||
|
TIM_Timer1_SetMode(mode);
|
||||||
|
if (mode == TIM_TimerMode_8BitAuto)
|
||||||
|
{
|
||||||
|
init = _TIM_InitValueCalculate(frequency, freq1t, 0xFF);
|
||||||
|
TIM_Timer1_SetInitValue(init & 0xFF, init & 0xFF);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
init = _TIM_InitValueCalculate(frequency, freq1t, 0xFFFF);
|
||||||
|
TIM_Timer1_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
}
|
||||||
|
EXTI_Timer1_SetIntState(intState);
|
||||||
|
EXTI_Timer1_SetIntPriority(intPriority);
|
||||||
|
}
|
||||||
|
|
||||||
|
int16_t _TIM_Timer234_InitValueCalculate(
|
||||||
|
uint16_t frequency, uint8_t prescaler, HAL_State_t freq1t)
|
||||||
|
{
|
||||||
|
uint32_t value = SYS_GetSysClk();
|
||||||
|
if (!freq1t)
|
||||||
|
value = value / 12;
|
||||||
|
value = value / ((prescaler + 1) * frequency);
|
||||||
|
|
||||||
|
if (value > 0xFFFF)
|
||||||
|
return 0;
|
||||||
|
else
|
||||||
|
return 0xFFFF - value;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Timer2,3,4 Configuration
|
||||||
|
*
|
||||||
|
* 1. no interrupt priority
|
||||||
|
* 2. frequency = SYSCLK / (TMxPS + 1) / (0xFFFF - TxH,TxL) / (1T? 1 : 12)
|
||||||
|
*/
|
||||||
|
|
||||||
|
void TIM_Timer2_Config(
|
||||||
|
HAL_State_t freq1t, uint8_t prescaler, uint16_t frequency, HAL_State_t intState)
|
||||||
|
{
|
||||||
|
uint16_t init = _TIM_Timer234_InitValueCalculate(frequency, prescaler, freq1t);
|
||||||
|
TIM_Timer2_Set1TMode(freq1t);
|
||||||
|
TIM_Timer2_SetPreScaler(prescaler);
|
||||||
|
TIM_Timer2_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
EXTI_Timer2_SetIntState(intState);
|
||||||
|
}
|
||||||
|
|
||||||
|
void TIM_Timer3_Config(
|
||||||
|
HAL_State_t freq1t, uint8_t prescaler, uint16_t frequency, HAL_State_t intState)
|
||||||
|
{
|
||||||
|
uint16_t init = _TIM_Timer234_InitValueCalculate(frequency, prescaler, freq1t);
|
||||||
|
TIM_Timer3_Set1TMode(freq1t);
|
||||||
|
TIM_Timer3_SetPreScaler(prescaler);
|
||||||
|
TIM_Timer3_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
EXTI_Timer3_SetIntState(intState);
|
||||||
|
}
|
||||||
|
|
||||||
|
void TIM_Timer4_Config(
|
||||||
|
HAL_State_t freq1t, uint8_t prescaler, uint16_t frequency, HAL_State_t intState)
|
||||||
|
{
|
||||||
|
uint16_t init = _TIM_Timer234_InitValueCalculate(frequency, prescaler, freq1t);
|
||||||
|
TIM_Timer4_Set1TMode(freq1t);
|
||||||
|
TIM_Timer4_SetPreScaler(prescaler);
|
||||||
|
TIM_Timer4_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
EXTI_Timer4_SetIntState(intState);
|
||||||
|
}
|
||||||
171
src/fw_uart.c
Normal file
171
src/fw_uart.c
Normal file
@ -0,0 +1,171 @@
|
|||||||
|
#include "fw_uart.h"
|
||||||
|
#include "fw_tim.h"
|
||||||
|
#include "fw_sys.h"
|
||||||
|
|
||||||
|
static const char hexTable[16] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'};
|
||||||
|
char wptr, rptr, UART1_RxBuffer[UART_RX_BUFF_SIZE];
|
||||||
|
__bit busy;
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* UART1
|
||||||
|
*/
|
||||||
|
int16_t _UART1_Timer_InitValueCalculate(HAL_State_t freq1t, uint32_t baudrate)
|
||||||
|
{
|
||||||
|
uint32_t value, sysclk = SYS_GetSysClk();
|
||||||
|
value = sysclk / (4 * baudrate);
|
||||||
|
if (!freq1t)
|
||||||
|
value = value / 12;
|
||||||
|
if (value > 0xFFFF)
|
||||||
|
return 0;
|
||||||
|
else
|
||||||
|
return 0xFFFF - value + 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt)
|
||||||
|
{
|
||||||
|
uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate);
|
||||||
|
UART1_SetBaudSource(baudSource);
|
||||||
|
// Timer1 configuration. Mode0 only, mode2 is covered by mode0 so it is unnecessary.
|
||||||
|
if (baudSource == UART1_BaudSource_Timer1)
|
||||||
|
{
|
||||||
|
TIM_Timer1_Set1TMode(freq1t);
|
||||||
|
TIM_Timer1_SetMode(TIM_TimerMode_16BitAuto);
|
||||||
|
TIM_Timer1_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
TIM_Timer1_SetRunState(HAL_State_ON);
|
||||||
|
}
|
||||||
|
// Timer2 configuration
|
||||||
|
else
|
||||||
|
{
|
||||||
|
// Timer2: 1T mode and initial value. prescaler is ignored, no interrupt.
|
||||||
|
TIM_Timer2_Set1TMode(freq1t);
|
||||||
|
TIM_Timer2_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
TIM_Timer2_SetRunState(HAL_State_ON);
|
||||||
|
}
|
||||||
|
if (enableInterrupt)
|
||||||
|
{
|
||||||
|
// Enable UART1 interrupt
|
||||||
|
EXTI_Global_SetIntState(HAL_State_ON);
|
||||||
|
EXTI_UART1_SetIntState(HAL_State_ON);
|
||||||
|
EXTI_UART1_SetIntPriority(EXTI_IntPriority_Highest);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_ConfigMode1Dyn8bitUart(
|
||||||
|
UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt)
|
||||||
|
{
|
||||||
|
SM0=0; SM1=1;
|
||||||
|
_UART1_ConfigDynUart(baudSource, freq1t, baudrate, enableInterrupt);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_ConfigMode3Dyn9bitUart(
|
||||||
|
UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt)
|
||||||
|
{
|
||||||
|
SM0=1; SM1=1;
|
||||||
|
_UART1_ConfigDynUart(baudSource, freq1t, baudrate, enableInterrupt);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_InterruptHandler(void)
|
||||||
|
{
|
||||||
|
if (TI)
|
||||||
|
{
|
||||||
|
TI = 0;
|
||||||
|
busy = 0;
|
||||||
|
}
|
||||||
|
if (RI)
|
||||||
|
{
|
||||||
|
RI = 0;
|
||||||
|
UART1_RxBuffer[rptr++] = SBUF;
|
||||||
|
rptr = rptr % UART_RX_BUFF_SIZE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_IntTxChar(char dat)
|
||||||
|
{
|
||||||
|
while (busy);
|
||||||
|
busy = 1;
|
||||||
|
SBUF = dat;
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_IntTxHex(uint8_t hex)
|
||||||
|
{
|
||||||
|
UART1_IntTxChar(hexTable[hex >> 4]);
|
||||||
|
UART1_IntTxChar(hexTable[hex & 0xF]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_IntTxString(uint8_t *str)
|
||||||
|
{
|
||||||
|
while (*str) UART1_IntTxChar(*str++);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_TxChar(char dat)
|
||||||
|
{
|
||||||
|
SBUF = dat;
|
||||||
|
while(!TI);
|
||||||
|
SBIT_RESET(TI);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_TxHex(uint8_t hex)
|
||||||
|
{
|
||||||
|
UART1_TxChar(hexTable[hex >> 4]);
|
||||||
|
UART1_TxChar(hexTable[hex & 0xF]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_TxString(uint8_t *str)
|
||||||
|
{
|
||||||
|
while (*str) UART1_TxChar(*str++);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/***************************** /
|
||||||
|
* UART2
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _UART2_ConfigDynUart(HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt)
|
||||||
|
{
|
||||||
|
uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate);
|
||||||
|
// Timer2: 1T mode and initial value. prescaler is ignored, no interrupt.
|
||||||
|
TIM_Timer2_Set1TMode(freq1t);
|
||||||
|
TIM_Timer2_SetInitValue(init >> 8, init & 0xFF);
|
||||||
|
TIM_Timer2_SetRunState(HAL_State_ON);
|
||||||
|
if (enableInterrupt)
|
||||||
|
{
|
||||||
|
// Enable UART1 interrupt
|
||||||
|
EXTI_Global_SetIntState(HAL_State_ON);
|
||||||
|
EXTI_UART2_SetIntState(HAL_State_ON);
|
||||||
|
EXTI_UART2_SetIntPriority(EXTI_IntPriority_Highest);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART2_ConfigMode0Dyn8bitUart(
|
||||||
|
HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt)
|
||||||
|
{
|
||||||
|
SFR_RESET(S2CON, 7);
|
||||||
|
_UART2_ConfigDynUart(freq1t, baudrate, enableInterrupt);
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* Mode1: 9-bit UART, dynamic baud-rate, provided by Timer2
|
||||||
|
*/
|
||||||
|
void UART2_ConfigMode1Dyn9bitUart(
|
||||||
|
HAL_State_t freq1t, uint32_t baudrate, HAL_State_t enableInterrupt)
|
||||||
|
{
|
||||||
|
SFR_SET(S2CON, 7);
|
||||||
|
_UART2_ConfigDynUart(freq1t, baudrate, enableInterrupt);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART2_TxChar(char dat)
|
||||||
|
{
|
||||||
|
S2BUF = dat;
|
||||||
|
while(!(S2CON & B00000010));
|
||||||
|
SFR_RESET(S2CON, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART2_TxHex(uint8_t hex)
|
||||||
|
{
|
||||||
|
UART2_TxChar(hexTable[hex >> 4]);
|
||||||
|
UART2_TxChar(hexTable[hex & 0xF]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART2_TxString(uint8_t *str)
|
||||||
|
{
|
||||||
|
while (*str) UART2_TxChar(*str++);
|
||||||
|
}
|
||||||
113
src/fw_util.c
Normal file
113
src/fw_util.c
Normal file
@ -0,0 +1,113 @@
|
|||||||
|
#include "fw_util.h"
|
||||||
|
#include "fw_sys.h"
|
||||||
|
|
||||||
|
|
||||||
|
void UTIL_Uart1_24M_9600_Init(void)
|
||||||
|
{
|
||||||
|
SCON = 0x50; //8 bits and variable baudrate
|
||||||
|
AUXR |= 0x40; //imer clock is 1T mode
|
||||||
|
AUXR &= 0xFE; //UART 1 use Timer1 as baudrate generator
|
||||||
|
TMOD &= 0x0F; //Set timer work mode
|
||||||
|
TL1 = 0x8F; //Initial timer value
|
||||||
|
TH1 = 0xFD; //Initial timer value
|
||||||
|
ET1 = 0; //Disable Timer%d interrupt
|
||||||
|
TR1 = 1; //Timer1 start run
|
||||||
|
}
|
||||||
|
|
||||||
|
void UTIL_Uart1_24M_115200_Init(void)
|
||||||
|
{
|
||||||
|
SCON = 0x50; //8 bits and variable baudrate
|
||||||
|
AUXR |= 0x40; //imer clock is 1T mode
|
||||||
|
AUXR &= 0xFE; //UART 1 use Timer1 as baudrate generator
|
||||||
|
TMOD &= 0x0F; //Set timer work mode
|
||||||
|
TL1 = 0xCC; //Initial timer value
|
||||||
|
TH1 = 0xFF; //Initial timer value
|
||||||
|
ET1 = 0; //Disable Timer%d interrupt
|
||||||
|
TR1 = 1; //Timer1 start run
|
||||||
|
}
|
||||||
|
|
||||||
|
void UTIL_Uart1_33M1776_9600_Init(void)
|
||||||
|
{
|
||||||
|
SCON = 0x50; //8 bits and variable baudrate
|
||||||
|
AUXR |= 0x40; //imer clock is 1T mode
|
||||||
|
AUXR &= 0xFE; //UART 1 use Timer1 as baudrate generator
|
||||||
|
TMOD &= 0x0F; //Set timer work mode
|
||||||
|
TL1 = 0xA0; //Initial timer value
|
||||||
|
TH1 = 0xFC; //Initial timer value
|
||||||
|
ET1 = 0; //Disable Timer%d interrupt
|
||||||
|
TR1 = 1; //Timer1 start run
|
||||||
|
}
|
||||||
|
|
||||||
|
void UTIL_Uart1_33M1776_115200_Init(void)
|
||||||
|
{
|
||||||
|
SCON = 0x50;
|
||||||
|
AUXR |= 0x40;
|
||||||
|
AUXR &= 0xFE;
|
||||||
|
TMOD &= 0x0F;
|
||||||
|
TL1 = 0xB8;
|
||||||
|
TH1 = 0xFF;
|
||||||
|
ET1 = 0;
|
||||||
|
TR1 = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void UTIL_Uart1_35M_9600_Init(void)
|
||||||
|
{
|
||||||
|
SCON = 0x50;
|
||||||
|
AUXR |= 0x40;
|
||||||
|
AUXR &= 0xFE;
|
||||||
|
TMOD &= 0x0F;
|
||||||
|
TL1 = 0x70;
|
||||||
|
TH1 = 0xFC;
|
||||||
|
ET1 = 0;
|
||||||
|
TR1 = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void UTIL_Uart1_36M864_9600_Init(void)
|
||||||
|
{
|
||||||
|
SCON = 0x50;
|
||||||
|
AUXR |= 0x40;
|
||||||
|
AUXR &= 0xFE;
|
||||||
|
TMOD &= 0x0F;
|
||||||
|
TL1 = 0x40;
|
||||||
|
TH1 = 0xFC;
|
||||||
|
ET1 = 0;
|
||||||
|
TR1 = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void UTIL_Uart1_36M864_115200_Init(void)
|
||||||
|
{
|
||||||
|
SCON = 0x50;
|
||||||
|
AUXR |= 0x40;
|
||||||
|
AUXR &= 0xFE;
|
||||||
|
TMOD &= 0x0F;
|
||||||
|
TL1 = 0xB0;
|
||||||
|
TH1 = 0xFF;
|
||||||
|
ET1 = 0;
|
||||||
|
TR1 = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void UTIL_ItrimScan(uint8_t ircband, uint8_t *str)
|
||||||
|
{
|
||||||
|
uint8_t i = 0xFF, j;
|
||||||
|
if (ircband & 0x01 > 0)
|
||||||
|
{
|
||||||
|
i = 0xDE;
|
||||||
|
}
|
||||||
|
do
|
||||||
|
{
|
||||||
|
j = 3;
|
||||||
|
do
|
||||||
|
{
|
||||||
|
SYS_SetFOSC(ircband, 0, i, j);
|
||||||
|
SYS_Delay(1);
|
||||||
|
// UTIL_PrintHex(IRCBAND);
|
||||||
|
// UTIL_PrintChar(' ');
|
||||||
|
// UTIL_PrintHex(IRTRIM);
|
||||||
|
// UTIL_PrintChar(0x20);
|
||||||
|
// UTIL_PrintHex(LIRTRIM);
|
||||||
|
// UTIL_PrintChar(0x20);
|
||||||
|
// UTIL_PrintString(str);
|
||||||
|
SYS_Delay(5);
|
||||||
|
} while (j--);
|
||||||
|
} while (i--);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue
Block a user