149 lines
6.7 KiB
C
Executable File
149 lines
6.7 KiB
C
Executable File
// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __FW_RNF24L01_H__
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#define __FW_RNF24L01_H__
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#include "fw_hal.h"
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#define NRF_CSN P35
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#define NRF_MOSI P34
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#define NRF_MISO P33
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#define NRF_SCK P32
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#define NRF_IRQ P36
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#define NRF_CE P37
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/********** SPI(nRF24L01) commands ***********/
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//
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#define NRF24_CMD_R_REGISTER 0x00 // [000A AAAA] Register read
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#define NRF24_CMD_W_REGISTER 0x20 // [001A AAAA] Register write
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#define NRF24_CMD_R_RX_PAYLOAD 0x61 // Read RX payload
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#define NRF24_CMD_W_TX_PAYLOAD 0xA0 // Write TX payload
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#define NRF24_CMD_FLUSH_TX 0xE1 // Flush TX FIFO
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#define NRF24_CMD_FLUSH_RX 0xE2 // Flush RX FIFO
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#define NRF24_CMD_REUSE_TX_PL 0xE3 // Reuse TX payload
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#define NRF24_CMD_R_RX_PL_WID 0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO.
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#define NRF24_CMD_W_ACK_PAYLOAD 0xA8 // [1010 1PPP] Write ACK Payload to be with ACK packet on PIPE PPP
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#define NRF24_CMD_W_TX_PAYLOAD_NOACK 0xB0 //Write TX payload and disable AUTOACK
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#define NRF24_CMD_NOP 0xFF // No operation (used for reading status register)
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#define NRF24_CMD_ACTIVATE 0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features
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#define NRF24_CMD_LOCK_UNLOCK 0x50 // Lock/unlock exclusive features
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// SPI(nRF24L01) register address definitions
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#define NRF24_REG_CONFIG 0x00 // Configuration register
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#define NRF24_REG_EN_AA 0x01 // Enable "Auto acknowledgment"
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#define NRF24_REG_EN_RXADDR 0x02 // Enable RX addresses
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#define NRF24_REG_SETUP_AW 0x03 // Setup of address widths
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#define NRF24_REG_SETUP_RETR 0x04 // Setup of automatic re-transmit
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#define NRF24_REG_RF_CH 0x05 // RF channel
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#define NRF24_REG_RF_SETUP 0x06 // RF setup
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#define NRF24_REG_STATUS 0x07 // Status register
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#define NRF24_REG_OBSERVE_TX 0x08 // Transmit observe register
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#define NRF24_REG_RPD 0x09 // Received power detector
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#define NRF24_REG_RX_ADDR_P0 0x0A // Receive address data pipe 0
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#define NRF24_REG_RX_ADDR_P1 0x0B // Receive address data pipe 1
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#define NRF24_REG_RX_ADDR_P2 0x0C // Receive address data pipe 2
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#define NRF24_REG_RX_ADDR_P3 0x0D // Receive address data pipe 3
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#define NRF24_REG_RX_ADDR_P4 0x0E // Receive address data pipe 4
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#define NRF24_REG_RX_ADDR_P5 0x0F // Receive address data pipe 5
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#define NRF24_REG_TX_ADDR 0x10 // Transmit address
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#define NRF24_REG_RX_PW_P0 0x11 // Number of bytes in RX payload in data pipe 0
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#define NRF24_REG_RX_PW_P1 0x12 // Number of bytes in RX payload in data pipe 1
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#define NRF24_REG_RX_PW_P2 0x13 // Number of bytes in RX payload in data pipe 2
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#define NRF24_REG_RX_PW_P3 0x14 // Number of bytes in RX payload in data pipe 3
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#define NRF24_REG_RX_PW_P4 0x15 // Number of bytes in RX payload in data pipe 4
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#define NRF24_REG_RX_PW_P5 0x16 // Number of bytes in RX payload in data pipe 5
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#define NRF24_REG_FIFO_STATUS 0x17 // FIFO status register
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#define NRF24_REG_DYNPD 0x1C // Enable dynamic payload length
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#define NRF24_REG_FEATURE 0x1D // Feature register
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// Register bits definitions
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#define NRF24_CONFIG_PRIM_RX 0x01 // PRIM_RX bit in CONFIG register
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#define NRF24_CONFIG_PWR_UP 0x02 // PWR_UP bit in CONFIG register
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#define NRF24_FEATURE_EN_DYN_ACK 0x01 // EN_DYN_ACK bit in FEATURE register
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#define NRF24_FEATURE_EN_ACK_PAY 0x02 // EN_ACK_PAY bit in FEATURE register
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#define NRF24_FEATURE_EN_DPL 0x04 // EN_DPL bit in FEATURE register
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#define NRF24_FLAG_RX_DREADY 0x40 // RX_DR bit (data ready RX FIFO interrupt)
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#define NRF24_FLAG_TX_DSENT 0x20 // TX_DS bit (data sent TX FIFO interrupt)
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#define NRF24_FLAG_MAX_RT 0x10 // MAX_RT bit (maximum number of TX re-transmits interrupt)
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#define NRF24_FLAG_TX_FULL 0x01 // 1:TX FIFO full
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// Register masks definitions
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#define NRF24_MASK_REG_MAP 0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands
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#define NRF24_MASK_CRC 0x0C // Mask for CRC bits [3:2] in CONFIG register
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#define NRF24_MASK_STATUS_IRQ 0x70 // Mask for all IRQ bits in STATUS register
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#define NRF24_MASK_RF_PWR 0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register
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#define NRF24_MASK_RX_P_NO 0x0E // Mask RX_P_NO[3:1] bits in STATUS register
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#define NRF24_MASK_DATARATE 0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register
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#define NRF24_MASK_EN_RX 0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register
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#define NRF24_MASK_RX_PW 0x3F // Mask [5:0] bits in RX_PW_Px register
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#define NRF24_MASK_RETR_ARD 0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register
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#define NRF24_MASK_RETR_ARC 0x0F // Mask for ARC[3:0] bits in SETUP_RETR register
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#define NRF24_MASK_RXFIFO 0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register
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#define NRF24_MASK_TXFIFO 0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register
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#define NRF24_MASK_PLOS_CNT 0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register
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#define NRF24_MASK_ARC_CNT 0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register
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#define NRF24_ADDR_WIDTH 5 // RX/TX address width
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#define NRF24_PLOAD_WIDTH 32 // Payload width
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#define NRF24_TEST_ADDR "nRF24"
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typedef enum
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{
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NRF24_MODE_RX = 0x00,
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NRF24_MODE_TX = 0x01
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} NRF24_MODE;
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typedef enum
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{
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NRF24_SCEN_RX = 0x00,
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NRF24_SCEN_TX = 0x01,
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NRF24_SCEN_HALF_DUPLEX = 0x02
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} NRF24_SCEN;
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void NRF24L01_WriteReg(uint8_t reg, uint8_t value);
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uint8_t NRF24L01_ReadReg(uint8_t reg);
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void NRF24L01_ReadToBuf(uint8_t reg, uint8_t *pBuf, uint8_t len);
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void NRF24L01_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len);
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void NRF24L01_PrintBuf(uint8_t *buf);
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/**
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* Flush the RX FIFO
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*/
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void NRF24L01_FlushRX(void);
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/**
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* Flush the TX FIFO
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*/
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void NRF24L01_FlushTX(void);
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void NRF24L01_CheckFlag(uint8_t *tx_ds, uint8_t *max_rt, uint8_t *rx_dr);
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uint8_t NRF24L01_RxAvailable(uint8_t* pipe_num);
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void NRF24L01_HandelIrqFlag(uint8_t *buf);
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void NRF24L01_Tx(uint8_t *txbuf);
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void NRF24L01_StartFastWrite(const void* txbuf);
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uint8_t NRF24L01_WriteFast(const void* txbuf);
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void NRF24L01_ResetTX(void);
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uint8_t NRF24L01_Check(void);
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void NRF24L01_Init(NRF24_MODE mode);
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#endif |