98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ___FW_SPI_H___
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#define ___FW_SPI_H___
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#include "fw_conf.h"
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#include "fw_types.h"
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/**
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* STC8H1K08(TSSOP20) STC8H3K32S2(TSSOP20)
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* #1 #4 #1 #3 #4
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* SPI SS -> 1 16 19 7 16(P35)
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* SPI MOSI -> 2 15 15(P34)
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* SPI MISO -> 3 14 14(P33)
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* SPI CLK -> 4 13 13(P32)
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*
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* The ports for STC8G1K08-8Pin, STC8G1K08A are different:
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* SS MO MI SCLK
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* 00 - P5.5 P5.4 P3.3 P3.2, 01/10/11 - n/a
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*/
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typedef enum
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{
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// SS MOSI MISO SCLK
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SPI_AlterPort_P12P54_P13_P14_P15 = 0x00,
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SPI_AlterPort_P22_P23_P24_P25 = 0x01,
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SPI_AlterPort_P54_P40_P41_P43 = 0x02,
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SPI_AlterPort_P35_P34_P33_P32 = 0x03,
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SPI_AlterPort_8G1K08_8Pin = 0x00,
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} SPI_AlterPort_t;
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typedef enum
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{
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SPI_ClockPreScaler_4 = 0x00,
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SPI_ClockPreScaler_8 = 0x01,
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SPI_ClockPreScaler_16 = 0x02,
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SPI_ClockPreScaler_32or2 = 0x03,
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} SPI_ClockPreScaler_t;
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typedef enum
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{
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SPI_ClockPhase_LeadingEdge = 0x00, // Bits are sampled on the leading edge of SCLK
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SPI_ClockPhase_TrailingEdge = 0x01, // Bits are sampled on the trailing edge of SCLK
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} SPI_ClockPhase_t;
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typedef enum
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{
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SPI_DataOrder_MSB = 0x00, // High bits first
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SPI_DataOrder_LSB = 0x01, // Low bits first
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} SPI_DataOrder_t;
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#define SPI_RxTxFinished() (SPSTAT & 0x80)
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#define SPI_ClearInterrupt() SFR_SET(SPSTAT, 7)
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#define SPI_ClearWriteConflictInterrupt() SFR_SET(SPSTAT, 6)
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#define SPI_ClearInterrupts() (SPSTAT |= 0xC0)
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#define SPI_IgnoreSlaveSelect(__STATE__) SFR_ASSIGN(SPCTL, 7, __STATE__)
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#define SPI_SetEnabled(__STATE__) SFR_ASSIGN(SPCTL, 6, __STATE__)
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#define SPI_SetDataOrder(__ORDER__) SFR_ASSIGN(SPCTL, 5, __ORDER__)
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#define SPI_SetMasterMode(__STATE__) SFR_ASSIGN(SPCTL, 4, __STATE__)
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/**
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* Clock Polarity, CPOL
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* 0: clock line idles low
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* 1: clock line idles high
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*/
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#define SPI_SetClockPolarity(__STATE__) SFR_ASSIGN(SPCTL, 3, __STATE__)
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/**
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* Clock Phase (CPHA)
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* 0: bits are sampled on the leading clock edge
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* 1: bits are sampled on the trailing clock edge
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*/
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#define SPI_SetClockPhase(__PHASE__) SFR_ASSIGN(SPCTL, 2, __PHASE__)
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/**
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* SPI Clock
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*/
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#define SPI_SetClockPrescaler(__PRE_SCALER__) (SPCTL = SPCTL & ~0x03 | ((__PRE_SCALER__) << 0))
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/**
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* Alternative ports
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*/
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#define SPI_SetPort(__ALTER_PORT__) (P_SW1 = P_SW1 & ~(0x03 << 2) | ((__ALTER_PORT__) << 2))
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uint8_t SPI_TxRx(uint8_t dat);
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void SPI_TxRxBytes(uint8_t *pBuf, uint8_t len);
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#endif
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