diff --git a/demo/pwm/pwm_dac_voice/main.c b/demo/pwm/pwm_dac_voice/main.c index 0185bf6..a6b1053 100644 --- a/demo/pwm/pwm_dac_voice/main.c +++ b/demo/pwm/pwm_dac_voice/main.c @@ -16,9 +16,8 @@ * Demo: DAC voice output simulation * Board: STC8H3K32 (types with flash size >= 32KB) * - * P1.0 -> Speaker + // if speaker impedance is less than 8 ohms, - * wire a 5 ohm resistance between P1.0 and speaker - * GND -> Speaker - + * P1.0 -> 200R -> Speaker + + * GND -> Speaker - */ #include "fw_hal.h" #include "voice.h" diff --git a/demo/spi/nrf24l01_audio/main.c b/demo/spi/nrf24l01_audio/main.c new file mode 100644 index 0000000..97e841c --- /dev/null +++ b/demo/spi/nrf24l01_audio/main.c @@ -0,0 +1,351 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * Example code of wireless audio transer with NRF24L01 module + * + * Pin connection: + * 8H3K32S2/8H1K08 NRF24L01 + * P35(SS, Ignored) => CSN 16 + * P34(MOSI) => MOSI 15 + * P33(MISO) => MISO 14 + * P32(SPCLK) => CLK 13 + * P36(INT2) => IRQ 17 + * P37(IO) => CE 18 + * + * TX: STC8H3K32S2 MAX9814 + * P11(ADC1) => MIC + * 3.3V => VDD + * 3.3V => GAIN + * GND => A/R + * GND => GND + * + * RX: STC8H1K08 PAM8403 + * P10(PWM1P) => 200R => L or R Input + * GND => _|_ Input + * Ext 3.3V/5V => VCC + * Ext GND => GND + * + * Note: + * 1. Use individual power supply for PAM8403 + * 2. Switch RX_ADDRESS and TX_ADDRESS in nrf24l01.c for RX and TX + */ + +#include "nrf24l01.h" +//#include "voice.h" +#include + +#define BUFF_UNITS 8 +#define BUFF_SIZE (BUFF_UNITS * NRF24_PLOAD_WIDTH) + +const NRF24_SCEN CURRENT_SCEN = NRF24_SCEN_TX; +extern uint16_t NRF24L01_rxsn; +extern uint8_t *NRF24L01_xbuf_data; + +__XDATA uint8_t MAIN_buf[2][BUFF_SIZE] = {{0}}; +uint8_t MAIN_buf_index = 0, MAIN_buf_pos = 0, + MAIN_ready_index = 0xFF, + MAIN_txrx_index, MAIN_txrx_pos = 0; + +//uint16_t voice_pos = 0, voice_size = 10665; + +void ADC_Init(void) +{ + // Set ADC1(GPIO P1.1) HIP + GPIO_P1_SetMode(GPIO_Pin_1, GPIO_Mode_Input_HIP); + + // Channel: ADC1 + ADC_SetChannel(0x01); + // ADC Clock = SYSCLK / 2 / (1+2) = SYSCLK / 6 + ADC_SetClockPrescaler(0x02); + // Left alignment, high 8-bit in ADC_RES + ADC_SetResultAlignmentLeft(); + // Enable interrupts + EXTI_Global_SetIntState(HAL_State_ON); + EXTI_ADC_SetIntState(HAL_State_ON); + // Turn on ADC power + ADC_SetPowerState(HAL_State_ON); +} + +void SPI_Init(void) +{ + // MISO(P33) MOSI(P34) + GPIO_P3_SetMode(GPIO_Pin_4, GPIO_Mode_InOut_QBD); + // SCLK(P32) CSN(P35) CE(P37) + GPIO_P3_SetMode(GPIO_Pin_2|GPIO_Pin_5|GPIO_Pin_7, GPIO_Mode_Output_PP); + // IRQ(P36) + GPIO_P3_SetMode(GPIO_Pin_6, GPIO_Mode_Input_HIP); + + // ST7567 doesn't work if SPI frequency is too high + SPI_SetClockPrescaler(SPI_ClockPreScaler_16); + // Clock idles low + SPI_SetClockPolarity(HAL_State_OFF); + // Data transfer is driven by lower SS pin + SPI_SetClockPhase(SPI_ClockPhase_LeadingEdge); + // MSB first + SPI_SetDataOrder(SPI_DataOrder_MSB); + // Define the output pins + SPI_SetPort(SPI_AlterPort_P35_P34_P33_P32); + // Ignore SS pin, use MSTR to swith between master/slave mode + SPI_IgnoreSlaveSelect(HAL_State_ON); + // Master mode + SPI_SetMasterMode(HAL_State_ON); + // Start SPI + SPI_SetEnabled(HAL_State_ON); +} + +void PWM_Init() +{ + // Set GPIO pins output mode P10 -> PWMA.1P + GPIO_P1_SetMode(GPIO_Pin_0, GPIO_Mode_Output_PP); + // Turn off PWMA.1 before change its mode + PWMA_PWM1_SetPortState(HAL_State_OFF); + PWMA_PWM1N_SetPortState(HAL_State_OFF); + // Set PWMA.1 port direction output + PWMA_PWM1_SetPortDirection(PWMB_PortDirOut); + // Set PWMA.1 output low voltage when counter is less than target value + PWMA_PWM1_ConfigOutputMode(PWM_OutputMode_PWM_HighIfLess); + // Enable comparison value preload to make duty cycle changing smooth + PWMA_PWM1_SetComparePreload(HAL_State_ON); + // Turn on PWMA.1 + PWMA_PWM1_SetPortState(HAL_State_ON); + + // Set PWM frequency to 16kHz, Fpwm = SYSCLK / (PWMx_PSCR + 1) / (PWMx_ARR + 1) + PWMA_SetPrescaler(8); + // PWM width = Period + 1 (side alignment), or AutoReloadPeriod * 2 (center alignment) + PWMA_SetPeriod(0xFF); + // Counter direction, down:from [PWMA_ARRH,PWMA_ARRL] to 0 + PWMA_SetCounterDirection(PWM_CounterDirection_Down); + // Enable preload on reload-period + PWMA_SetAutoReloadPreload(HAL_State_ON); + // Enable output on PWMA.1P + PWMA_SetPinOutputState(PWM_Pin_1, HAL_State_ON); + // Set PWMA.1 alternative ports to P1.0 and P1.1 + PWMA_PWM1_SetPort(PWMA_PWM1_AlterPort_P10_P11); + // Enable overall output + PWMA_SetOverallState(HAL_State_ON); + // Start counter + PWMA_SetCounterState(HAL_State_ON); +} + +void Timer0_Init() +{ + TIM_Timer0_Config(HAL_State_ON, TIM_TimerMode_16BitAuto, 8000); + EXTI_Timer0_SetIntState(HAL_State_ON); + EXTI_Timer0_SetIntPriority(EXTI_IntPriority_High); + EXTI_Global_SetIntState(HAL_State_ON); + TIM_Timer0_SetRunState(HAL_State_ON); +} + +void INT_Init() +{ + EXTI_Int2_SetIntState(HAL_State_ON); + EXTI_Global_SetIntState(HAL_State_ON); +} + +INTERRUPT(ADC_Routine, EXTI_VectADC) +{ + ADC_ClearInterrupt(); + MAIN_buf[MAIN_buf_index][MAIN_buf_pos] = ADC_RES; + if (MAIN_buf_pos == BUFF_SIZE - 1) + { + MAIN_buf_pos = 0; + MAIN_ready_index = MAIN_buf_index; + MAIN_buf_index = 1 - MAIN_buf_index; + } + else + { + MAIN_buf_pos++; + } +} + +INTERRUPT(Timer0_Routine, EXTI_VectTimer0) +{ + uint8_t dc; + if (CURRENT_SCEN == NRF24_SCEN_TX) + { + ADC_Start(); + // MAIN_buf[MAIN_buf_index][MAIN_buf_pos] = voice_bulk[voice_pos++]; + // if (MAIN_buf_pos == BUFF_SIZE - 1) + // { + // MAIN_buf_pos = 0; + // MAIN_ready_index = MAIN_buf_index; + // MAIN_buf_index = 1 - MAIN_buf_index; + // } + // else + // { + // MAIN_buf_pos++; + // } + // if (voice_pos == voice_size) voice_pos = 0; + } + else if (CURRENT_SCEN == NRF24_SCEN_RX) + { + if (MAIN_txrx_index == 0xFF) + { + if (MAIN_ready_index != 0xFF) + { + MAIN_txrx_index = MAIN_ready_index; + MAIN_ready_index = 0xFF; + MAIN_txrx_pos = 0; + } + } + if (MAIN_txrx_index != 0xFF) + { + dc = MAIN_buf[MAIN_txrx_index][MAIN_txrx_pos]; + PWMA_PWM1_SetCaptureCompareValue(dc); + // UART1_TxHex(dc); + // if (MAIN_txrx_pos % 32 == 0) + // { + // UART1_TxString("\r\n"); + // } + if (MAIN_txrx_pos == BUFF_SIZE - 1) + { + MAIN_txrx_index = 0xFF; + if (MAIN_ready_index != 0xFF) + { + MAIN_txrx_index = MAIN_ready_index; + MAIN_ready_index = 0xFF; + MAIN_txrx_pos = 0; + } + } + else + { + MAIN_txrx_pos++; + } + } + } +} + +INTERRUPT(Int2_Routine, EXTI_VectInt2) +{ + uint8_t pipe_num, status, i, *j; + status = NRF24L01_HandelIrqFlag(); + pipe_num = (status >> 1) & 0x07; + if (pipe_num != 0x07) + { + i = NRF24_PLOAD_WIDTH; + j = NRF24L01_xbuf_data; + while (i--) + { + MAIN_buf[MAIN_buf_index][MAIN_buf_pos++] = *j++; + } + //UART1_TxHex(MAIN_buf_pos); + if (MAIN_buf_pos == 0) + { + MAIN_ready_index = MAIN_buf_index; + MAIN_buf_index = 1 - MAIN_buf_index; + } + } +} + +void main(void) +{ + uint8_t *tmp; + uint8_t pos = 0, succ = 0, err = 0, i; + + SYS_SetClock(); + + // UART1, baud 115200, baud source Timer1, 1T mode, no interrupt + UART1_Config8bitUart(UART1_BaudSource_Timer1, HAL_State_ON, 115200); + UART1_TxString("UART Initialized\r\n"); + + SPI_Init(); + UART1_TxString("SPI Initialized\r\n"); + + while (NRF24L01_Check() == 1) + { + UART1_TxString("Check failed\r\n"); + SYS_Delay(1000); + } + UART1_TxString("NRF24L01 Checked\r\n"); + + switch (CURRENT_SCEN) + { + case NRF24_SCEN_TX: + ADC_Init(); + UART1_TxString("ADC Initialized\r\n"); + + Timer0_Init(); + UART1_TxString("Timer0 Initialized\r\n"); + + NRF24L01_Init(NRF24_MODE_TX); + UART1_TxString("NRF24L01 Initialized\r\n"); + while (1) + { + if (MAIN_ready_index != 0xFF) + { + MAIN_txrx_index = MAIN_ready_index; + MAIN_ready_index = 0xFF; + for (pos = 0; pos < BUFF_UNITS; pos++) + { + tmp = (uint8_t *)MAIN_buf[MAIN_txrx_index] + (pos * NRF24_PLOAD_WIDTH); + // for (i = 0; i < 32; i++) + // { + // UART1_TxHex(*(tmp + i)); + // } + // UART1_TxString("\r\n"); + if (NRF24L01_WriteFast(tmp) == 0) + { + NRF24L01_ResetTX(); + err++; + } + else + { + succ++; + } + if (err >= 255 || succ >= 255) + { + UART1_TxHex(err); + UART1_TxHex(succ); + UART1_TxString("\r\n"); + err = 0; + succ = 0; + } + //SYS_Delay(1); + } + + } + } + break; + + case NRF24_SCEN_RX: + INT_Init(); + PWM_Init(); + Timer0_Init(); + UART1_TxString("Timer0 Initialized\r\n"); + NRF24L01_Init(NRF24_MODE_RX); + while (1) + { + UART1_TxHex(NRF24L01_rxsn >> 8); + UART1_TxHex(NRF24L01_rxsn & 0xFF); + UART1_TxString("\r\n"); + SYS_Delay(1000); + } + break; + + case NRF24_SCEN_HALF_DUPLEX: + NRF24L01_Init(NRF24_MODE_RX); + INT_Init(); + while (1) + { + NRF24L01_Tx(tmp); + SYS_Delay(1000); + } + break; + + default: + UART1_TxString("Unknown scen\r\n"); + break; + } +} \ No newline at end of file diff --git a/demo/spi/nrf24l01_audio/nrf24l01.c b/demo/spi/nrf24l01_audio/nrf24l01.c new file mode 100755 index 0000000..88edd56 --- /dev/null +++ b/demo/spi/nrf24l01_audio/nrf24l01.c @@ -0,0 +1,181 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "nrf24l01.h" + +uint8_t __IDATA NRF24L01_xbuf[NRF24_PLOAD_WIDTH + 1]; +uint8_t *NRF24L01_xbuf_data = NRF24L01_xbuf + 1; +uint16_t NRF24L01_rxsn = 0; +// T:0x22, R:0x65 +const uint8_t RX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x22}; +const uint8_t TX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x65}; + +void NRF24L01_WriteReg(uint8_t reg, uint8_t value) +{ + NRF_CSN = 0; + NRF24L01_xbuf[0] = reg; + NRF24L01_xbuf[1] = value; + SPI_TxRxBytes(NRF24L01_xbuf, 2); + NRF_CSN = 1; +} + +uint8_t NRF24L01_ReadReg(uint8_t reg) +{ + NRF_CSN = 0; + NRF24L01_xbuf[0] = reg; + NRF24L01_xbuf[1] = NRF24_CMD_NOP; + SPI_TxRxBytes(NRF24L01_xbuf, 2); + NRF_CSN = 1; + return NRF24L01_xbuf[1]; +} + +void NRF24L01_ReadToBuf(uint8_t reg, uint8_t len) +{ + NRF_CSN = 0; + memset(NRF24L01_xbuf, NRF24_CMD_NOP, NRF24_PLOAD_WIDTH + 1); + NRF24L01_xbuf[0] = reg; + SPI_TxRxBytes(NRF24L01_xbuf, len + 1); + NRF_CSN = 1; +} + +void NRF24L01_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len) +{ + NRF_CSN = 0; + NRF24L01_xbuf[0] = reg; + memcpy(NRF24L01_xbuf_data, pBuf, len); + SPI_TxRxBytes(NRF24L01_xbuf, len + 1); + NRF_CSN = 1; +} + +void NRF24L01_PrintBuf(void) +{ + uint8_t i; + for (i = 0; i < NRF24_PLOAD_WIDTH + 1; i++) + { + UART1_TxHex(NRF24L01_xbuf[i]); + } + UART1_TxString("\r\n"); +} + +/** +* Flush the RX FIFO +*/ +void NRF24L01_FlushRX(void) +{ + NRF24L01_WriteReg(NRF24_CMD_FLUSH_RX, NRF24_CMD_NOP); +} + +/** +* Flush the TX FIFO +*/ +void NRF24L01_FlushTX(void) +{ + NRF24L01_WriteReg(NRF24_CMD_FLUSH_TX, NRF24_CMD_NOP); +} + +void NRF24L01_CheckFlag(void) +{ + // Read the status & reset the flags + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_STATUS, NRF24_FLAG_RX_DREADY|NRF24_FLAG_TX_DSENT|NRF24_FLAG_MAX_RT); +} + +uint8_t NRF24L01_HandelIrqFlag(void) +{ + uint8_t status, tx_ds, max_rt, rx_dr, pipe_num; + NRF24L01_CheckFlag(); + status = NRF24L01_xbuf[0]; + pipe_num = (status >> 1) & 0x07; + if (pipe_num != 0x07) + { + NRF24L01_ReadToBuf(NRF24_CMD_R_RX_PAYLOAD, NRF24_PLOAD_WIDTH); + NRF24L01_rxsn++; + } + return status; +} + +void NRF24L01_Tx(uint8_t *pBuf) +{ + NRF_CE = 0; + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0E); + NRF24L01_WriteFromBuf(NRF24_CMD_W_TX_PAYLOAD, pBuf, NRF24_PLOAD_WIDTH); + NRF_CE = 1; + SYS_Delay(10); // for reliable DS state when SETUP_RETR is 0x13 + NRF_CE = 0; + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0F); + NRF_CE = 1; +} + +void NRF24L01_StartFastWrite(const void* pBuf) +{ + NRF24L01_WriteFromBuf(NRF24_CMD_W_TX_PAYLOAD, pBuf, NRF24_PLOAD_WIDTH); + NRF_CE = 1; +} + +uint8_t NRF24L01_WriteFast(const void* pBuf) +{ + //Blocking only if FIFO is full. This will loop and block until TX is successful or fail + while ((NRF24L01_ReadReg(NRF24_REG_STATUS) & NRF24_FLAG_TX_FULL)) { + if (NRF24L01_xbuf[0] & NRF24_FLAG_MAX_RT) { + return 0; + } + } + NRF24L01_StartFastWrite(pBuf); + return 1; +} + +void NRF24L01_ResetTX(void) +{ + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_STATUS, NRF24_FLAG_MAX_RT);//Clear max retry flag + NRF_CE = 0; + NRF_CE = 1; +} + +uint8_t NRF24L01_Check(void) +{ + uint8_t i; + const uint8_t *ptr = (const uint8_t *)NRF24_TEST_ADDR; + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER | NRF24_REG_TX_ADDR, ptr, NRF24_ADDR_WIDTH); + NRF24L01_ReadToBuf(NRF24_CMD_R_REGISTER | NRF24_REG_TX_ADDR, NRF24_ADDR_WIDTH); + for (i = 0; i < NRF24_ADDR_WIDTH; i++) { + UART1_TxHex(*(NRF24L01_xbuf_data + i)); + if (*(NRF24L01_xbuf_data + i) != *ptr++) return 1; + } + return 0; +} + +void NRF24L01_Init(NRF24_MODE mode) +{ + NRF_CE = 0; + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_TX_ADDR, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RX_PW_P0, NRF24_PLOAD_WIDTH); + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_RX_ADDR_P0, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RX_PW_P1, NRF24_PLOAD_WIDTH); + NRF24L01_WriteFromBuf(NRF24_CMD_W_REGISTER + NRF24_REG_RX_ADDR_P1, (uint8_t *)RX_ADDRESS, NRF24_ADDR_WIDTH); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_EN_AA, 0x3f); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_EN_RXADDR, 0x3f); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_SETUP_RETR, 0x13); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RF_CH, 40); + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_RF_SETUP, 0x07); + switch (mode) + { + case NRF24_MODE_TX: + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0E); + break; + case NRF24_MODE_RX: + default: + NRF24L01_WriteReg(NRF24_CMD_W_REGISTER + NRF24_REG_CONFIG, 0x0F); + break; + } + NRF_CE = 1; +} \ No newline at end of file diff --git a/demo/spi/nrf24l01_audio/nrf24l01.h b/demo/spi/nrf24l01_audio/nrf24l01.h new file mode 100755 index 0000000..eaa6376 --- /dev/null +++ b/demo/spi/nrf24l01_audio/nrf24l01.h @@ -0,0 +1,150 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __FW_RNF24L01_H__ +#define __FW_RNF24L01_H__ + +#include "fw_hal.h" +#include "string.h" + +#define NRF_CSN P35 +#define NRF_MOSI P34 +#define NRF_MISO P33 +#define NRF_SCK P32 +#define NRF_IRQ P36 +#define NRF_CE P37 + +/********** SPI(nRF24L01) commands ***********/ +// +#define NRF24_CMD_R_REGISTER 0x00 // [000A AAAA] Register read +#define NRF24_CMD_W_REGISTER 0x20 // [001A AAAA] Register write +#define NRF24_CMD_R_RX_PAYLOAD 0x61 // Read RX payload +#define NRF24_CMD_W_TX_PAYLOAD 0xA0 // Write TX payload +#define NRF24_CMD_FLUSH_TX 0xE1 // Flush TX FIFO +#define NRF24_CMD_FLUSH_RX 0xE2 // Flush RX FIFO +#define NRF24_CMD_REUSE_TX_PL 0xE3 // Reuse TX payload +#define NRF24_CMD_R_RX_PL_WID 0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO. +#define NRF24_CMD_W_ACK_PAYLOAD 0xA8 // [1010 1PPP] Write ACK Payload to be with ACK packet on PIPE PPP +#define NRF24_CMD_W_TX_PAYLOAD_NOACK 0xB0 //Write TX payload and disable AUTOACK +#define NRF24_CMD_NOP 0xFF // No operation (used for reading status register) + +#define NRF24_CMD_ACTIVATE 0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features +#define NRF24_CMD_LOCK_UNLOCK 0x50 // Lock/unlock exclusive features + +// SPI(nRF24L01) register address definitions +#define NRF24_REG_CONFIG 0x00 // Configuration register +#define NRF24_REG_EN_AA 0x01 // Enable "Auto acknowledgment" +#define NRF24_REG_EN_RXADDR 0x02 // Enable RX addresses +#define NRF24_REG_SETUP_AW 0x03 // Setup of address widths +#define NRF24_REG_SETUP_RETR 0x04 // Setup of automatic re-transmit +#define NRF24_REG_RF_CH 0x05 // RF channel +#define NRF24_REG_RF_SETUP 0x06 // RF setup +#define NRF24_REG_STATUS 0x07 // Status register +#define NRF24_REG_OBSERVE_TX 0x08 // Transmit observe register +#define NRF24_REG_RPD 0x09 // Received power detector +#define NRF24_REG_RX_ADDR_P0 0x0A // Receive address data pipe 0 +#define NRF24_REG_RX_ADDR_P1 0x0B // Receive address data pipe 1 +#define NRF24_REG_RX_ADDR_P2 0x0C // Receive address data pipe 2 +#define NRF24_REG_RX_ADDR_P3 0x0D // Receive address data pipe 3 +#define NRF24_REG_RX_ADDR_P4 0x0E // Receive address data pipe 4 +#define NRF24_REG_RX_ADDR_P5 0x0F // Receive address data pipe 5 +#define NRF24_REG_TX_ADDR 0x10 // Transmit address +#define NRF24_REG_RX_PW_P0 0x11 // Number of bytes in RX payload in data pipe 0 +#define NRF24_REG_RX_PW_P1 0x12 // Number of bytes in RX payload in data pipe 1 +#define NRF24_REG_RX_PW_P2 0x13 // Number of bytes in RX payload in data pipe 2 +#define NRF24_REG_RX_PW_P3 0x14 // Number of bytes in RX payload in data pipe 3 +#define NRF24_REG_RX_PW_P4 0x15 // Number of bytes in RX payload in data pipe 4 +#define NRF24_REG_RX_PW_P5 0x16 // Number of bytes in RX payload in data pipe 5 +#define NRF24_REG_FIFO_STATUS 0x17 // FIFO status register +#define NRF24_REG_DYNPD 0x1C // Enable dynamic payload length +#define NRF24_REG_FEATURE 0x1D // Feature register + +// Register bits definitions +#define NRF24_CONFIG_PRIM_RX 0x01 // PRIM_RX bit in CONFIG register +#define NRF24_CONFIG_PWR_UP 0x02 // PWR_UP bit in CONFIG register +#define NRF24_FEATURE_EN_DYN_ACK 0x01 // EN_DYN_ACK bit in FEATURE register +#define NRF24_FEATURE_EN_ACK_PAY 0x02 // EN_ACK_PAY bit in FEATURE register +#define NRF24_FEATURE_EN_DPL 0x04 // EN_DPL bit in FEATURE register +#define NRF24_FLAG_RX_DREADY 0x40 // RX_DR bit (data ready RX FIFO interrupt) +#define NRF24_FLAG_TX_DSENT 0x20 // TX_DS bit (data sent TX FIFO interrupt) +#define NRF24_FLAG_MAX_RT 0x10 // MAX_RT bit (maximum number of TX re-transmits interrupt) +#define NRF24_FLAG_TX_FULL 0x01 // 1:TX FIFO full + +// Register masks definitions +#define NRF24_MASK_REG_MAP 0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands +#define NRF24_MASK_CRC 0x0C // Mask for CRC bits [3:2] in CONFIG register +#define NRF24_MASK_STATUS_IRQ 0x70 // Mask for all IRQ bits in STATUS register +#define NRF24_MASK_RF_PWR 0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register +#define NRF24_MASK_RX_P_NO 0x0E // Mask RX_P_NO[3:1] bits in STATUS register +#define NRF24_MASK_DATARATE 0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register +#define NRF24_MASK_EN_RX 0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register +#define NRF24_MASK_RX_PW 0x3F // Mask [5:0] bits in RX_PW_Px register +#define NRF24_MASK_RETR_ARD 0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register +#define NRF24_MASK_RETR_ARC 0x0F // Mask for ARC[3:0] bits in SETUP_RETR register +#define NRF24_MASK_RXFIFO 0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register +#define NRF24_MASK_TXFIFO 0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register +#define NRF24_MASK_PLOS_CNT 0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register +#define NRF24_MASK_ARC_CNT 0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register + +#define NRF24_ADDR_WIDTH 5 // RX/TX address width +#define NRF24_PLOAD_WIDTH 32 // Payload width +#define NRF24_TEST_ADDR "nRF24" + +typedef enum +{ + NRF24_MODE_RX = 0x00, + NRF24_MODE_TX = 0x01 +} NRF24_MODE; + +typedef enum +{ + NRF24_SCEN_RX = 0x00, + NRF24_SCEN_TX = 0x01, + NRF24_SCEN_HALF_DUPLEX = 0x02 +} NRF24_SCEN; + + +void NRF24L01_WriteReg(uint8_t reg, uint8_t value); + +uint8_t NRF24L01_ReadReg(uint8_t reg); + +void NRF24L01_ReadToBuf(uint8_t reg, uint8_t len); + +void NRF24L01_WriteFromBuf(uint8_t reg, const uint8_t *pBuf, uint8_t len); + +void NRF24L01_PrintBuf(void); + +/** +* Flush the RX FIFO +*/ +void NRF24L01_FlushRX(void); + +/** +* Flush the TX FIFO +*/ +void NRF24L01_FlushTX(void); + +void NRF24L01_CheckFlag(void); +// uint8_t NRF24L01_RxAvailable(uint8_t* pipe_num); + +uint8_t NRF24L01_HandelIrqFlag(void); +void NRF24L01_Tx(uint8_t *pBuf); +void NRF24L01_StartFastWrite(const void* pBuf); +uint8_t NRF24L01_WriteFast(const void* pBuf); +void NRF24L01_ResetTX(void); +uint8_t NRF24L01_Check(void); +void NRF24L01_Init(NRF24_MODE mode); + + +#endif \ No newline at end of file