diff --git a/demo/pwm/pwm_2ch_complementary.c b/demo/pwm/pwm_2ch_complementary.c new file mode 100644 index 0000000..69d4065 --- /dev/null +++ b/demo/pwm/pwm_2ch_complementary.c @@ -0,0 +1,76 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * Demo: PWM 2-channel complementary output + * + * P1.0 -> 1k Ω resistor -> LED1+ + * P1.1 -> 1k Ω resistor -> LED2+ + * GND -> LED1- + * GND -> LED2- +*/ +#include "fw_hal.h" + + +void main(void) +{ + uint16_t dc = 0; + + SYS_SetClock(); + // UART1, baud 115200, baud source Timer2, 1T mode + UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_Timer2, HAL_State_ON, 115200); + + // Set GPIO pins output mode + GPIO_P1_SetMode(GPIO_Pin_0|GPIO_Pin_1, GPIO_Mode_Output_PP); + // Turn off PWMA.1 before change its mode + PWMA_PWM1_SetPortState(HAL_State_OFF); + PWMA_PWM1N_SetPortState(HAL_State_OFF); + // Set PWMA.1 port direction output + PWMA_PWM1_SetPortDirection(PWMB_PortDirOut); + // Set PWMA.1 output low voltage when counter is less than target value + PWMA_PWM1_SetOutputMode(PWM_OutputMode_PWM_LowIfLess); + // Enable comparison value preload to make duty cycle changing smooth + PWMA_PWM1_SetComparePreload(HAL_State_ON); + // Turn on PWMA.1 + PWMA_PWM1_SetPortState(HAL_State_ON); + // Turn on PWMA.1 complementary output + PWMA_PWM1N_SetPortState(HAL_State_ON); + // Set highest PWM clock + PWMA_SetPrescaler(0); + // PWM width = AutoReloadPeriod + 1 (side alignment), or AutoReloadPeriod * 2 (center alignment) + PWMA_SetAutoReloadPeriod(0xFF); + // Counter direction, down:from [PWMA_ARRH,PWMA_ARRL] to 0 + PWMA_SetCounterDirection(PWM_CounterDirection_Down); + // Enable preload on reload-period + PWMA_SetAutoReloadPeriodPreload(HAL_State_ON); + // Enable output on PWMA.1P, PWMA.1N + PWMA_SetPinOutputState(PWM_Pin_1|PWM_Pin_1N, HAL_State_ON); + // Set PWMA.1 alternative ports to P1.0 and P1.1 + PWMA_PWM1_SetPort(PWMA_PWM1_AlterPort_P10_P11); + // Enable overall output + PWMA_SetOverallState(HAL_State_ON); + // Start counter + PWMA_SetCounterState(HAL_State_ON); + + while(1) + { + PWMA_PWM1_SetCaptureCompareValue(dc); + UART1_TxHex(dc >> 8); + UART1_TxHex(dc & 0xFF); + dc++; + UART1_TxString("\r\n"); + if (dc == 0xFF) dc = 0; + SYS_Delay(10); + } +} \ No newline at end of file diff --git a/include/fw_exti.h b/include/fw_exti.h index 7f06ba0..2066736 100644 --- a/include/fw_exti.h +++ b/include/fw_exti.h @@ -103,39 +103,39 @@ typedef enum #define EXTI_INT_I2cSlvRxStop_ON SFRX_SET(I2CSLCR, 3) #define EXTI_INT_I2cSlvRxStop_OFF SFRX_RESET(I2CSLCR, 3) -#define EXTI_INT_PWM1_Break_ON SFRX_SET(PWM1_IER, 7) -#define EXTI_INT_PWM1_Break_OFF SFRX_RESET(PWM1_IER, 7) -#define EXTI_INT_PWM1_Int_ON SFRX_SET(PWM1_IER, 6) -#define EXTI_INT_PWM1_Int_OFF SFRX_RESET(PWM1_IER, 6) -#define EXTI_INT_PWM1_Comp_ON SFRX_SET(PWM1_IER, 5) -#define EXTI_INT_PWM1_Comp_OFF SFRX_RESET(PWM1_IER, 5) -#define EXTI_INT_PWM1_CapCH4_ON SFRX_SET(PWM1_IER, 4) -#define EXTI_INT_PWM1_CapCH4_OFF SFRX_RESET(PWM1_IER, 4) -#define EXTI_INT_PWM1_CapCH3_ON SFRX_SET(PWM1_IER, 3) -#define EXTI_INT_PWM1_CapCH3_OFF SFRX_RESET(PWM1_IER, 3) -#define EXTI_INT_PWM1_CapCH2_ON SFRX_SET(PWM1_IER, 2) -#define EXTI_INT_PWM1_CapCH2_OFF SFRX_RESET(PWM1_IER, 2) -#define EXTI_INT_PWM1_CapCH1_OFF SFRX_SET(PWM1_IER, 1) -#define EXTI_INT_PWM1_CapCH1_ON SFRX_RESET(PWM1_IER, 1) -#define EXTI_INT_PWM1_Update_OFF SFRX_SET(PWM1_IER, 0) -#define EXTI_INT_PWM1_Update_ON SFRX_RESET(PWM1_IER, 0) +#define EXTI_INT_PWMA_Break_ON SFRX_SET(PWMA_IER, 7) +#define EXTI_INT_PWMA_Break_OFF SFRX_RESET(PWMA_IER, 7) +#define EXTI_INT_PWMA_Int_ON SFRX_SET(PWMA_IER, 6) +#define EXTI_INT_PWMA_Int_OFF SFRX_RESET(PWMA_IER, 6) +#define EXTI_INT_PWMA_Comp_ON SFRX_SET(PWMA_IER, 5) +#define EXTI_INT_PWMA_Comp_OFF SFRX_RESET(PWMA_IER, 5) +#define EXTI_INT_PWMA_CapCH4_ON SFRX_SET(PWMA_IER, 4) +#define EXTI_INT_PWMA_CapCH4_OFF SFRX_RESET(PWMA_IER, 4) +#define EXTI_INT_PWMA_CapCH3_ON SFRX_SET(PWMA_IER, 3) +#define EXTI_INT_PWMA_CapCH3_OFF SFRX_RESET(PWMA_IER, 3) +#define EXTI_INT_PWMA_CapCH2_ON SFRX_SET(PWMA_IER, 2) +#define EXTI_INT_PWMA_CapCH2_OFF SFRX_RESET(PWMA_IER, 2) +#define EXTI_INT_PWMA_CapCH1_OFF SFRX_SET(PWMA_IER, 1) +#define EXTI_INT_PWMA_CapCH1_ON SFRX_RESET(PWMA_IER, 1) +#define EXTI_INT_PWMA_Update_OFF SFRX_SET(PWMA_IER, 0) +#define EXTI_INT_PWMA_Update_ON SFRX_RESET(PWMA_IER, 0) -#define EXTI_INT_PWM2_Break_ON SFRX_SET(PWM2_IER, 7) -#define EXTI_INT_PWM2_Break_OFF SFRX_RESET(PWM2_IER, 7) -#define EXTI_INT_PWM2_Int_ON SFRX_SET(PWM2_IER, 6) -#define EXTI_INT_PWM2_Int_OFF SFRX_RESET(PWM2_IER, 6) -#define EXTI_INT_PWM2_Comp_ON SFRX_SET(PWM2_IER, 5) -#define EXTI_INT_PWM2_Comp_OFF SFRX_RESET(PWM2_IER, 5) -#define EXTI_INT_PWM2_CapCH4_ON SFRX_SET(PWM2_IER, 4) -#define EXTI_INT_PWM2_CapCH4_OFF SFRX_RESET(PWM2_IER, 4) -#define EXTI_INT_PWM2_CapCH3_ON SFRX_SET(PWM2_IER, 3) -#define EXTI_INT_PWM2_CapCH3_OFF SFRX_RESET(PWM2_IER, 3) -#define EXTI_INT_PWM2_CapCH2_ON SFRX_SET(PWM2_IER, 2) -#define EXTI_INT_PWM2_CapCH2_OFF SFRX_RESET(PWM2_IER, 2) -#define EXTI_INT_PWM2_CapCH1_OFF SFRX_SET(PWM2_IER, 1) -#define EXTI_INT_PWM2_CapCH1_ON SFRX_RESET(PWM2_IER, 1) -#define EXTI_INT_PWM2_Update_OFF SFRX_SET(PWM2_IER, 0) -#define EXTI_INT_PWM2_Update_ON SFRX_RESET(PWM2_IER, 0) +#define EXTI_INT_PWMB_Break_ON SFRX_SET(PWMB_IER, 7) +#define EXTI_INT_PWMB_Break_OFF SFRX_RESET(PWMB_IER, 7) +#define EXTI_INT_PWMB_Int_ON SFRX_SET(PWMB_IER, 6) +#define EXTI_INT_PWMB_Int_OFF SFRX_RESET(PWMB_IER, 6) +#define EXTI_INT_PWMB_Comp_ON SFRX_SET(PWMB_IER, 5) +#define EXTI_INT_PWMB_Comp_OFF SFRX_RESET(PWMB_IER, 5) +#define EXTI_INT_PWMB_CapCH4_ON SFRX_SET(PWMB_IER, 4) +#define EXTI_INT_PWMB_CapCH4_OFF SFRX_RESET(PWMB_IER, 4) +#define EXTI_INT_PWMB_CapCH3_ON SFRX_SET(PWMB_IER, 3) +#define EXTI_INT_PWMB_CapCH3_OFF SFRX_RESET(PWMB_IER, 3) +#define EXTI_INT_PWMB_CapCH2_ON SFRX_SET(PWMB_IER, 2) +#define EXTI_INT_PWMB_CapCH2_OFF SFRX_RESET(PWMB_IER, 2) +#define EXTI_INT_PWMB_CapCH1_OFF SFRX_SET(PWMB_IER, 1) +#define EXTI_INT_PWMB_CapCH1_ON SFRX_RESET(PWMB_IER, 1) +#define EXTI_INT_PWMB_Update_OFF SFRX_SET(PWMB_IER, 0) +#define EXTI_INT_PWMB_Update_ON SFRX_RESET(PWMB_IER, 0) #define EXTI_INT_LCM_ON SFRX_SET(LCMIFCFG, 7) #define EXTI_INT_LCM_OFF SFRX_RESET(LCMIFCFG, 7) @@ -153,8 +153,8 @@ typedef enum #define EXTI_UART2_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 0, __PRIORITY__) #define EXTI_SPI_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 1, __PRIORITY__) -#define EXTI_PWM1_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 2, __PRIORITY__) -#define EXTI_PWM2_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 3, __PRIORITY__) +#define EXTI_PWMA_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 2, __PRIORITY__) +#define EXTI_PWMB_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 3, __PRIORITY__) #define EXTI_Int4_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 4, __PRIORITY__) #define EXTI_CMP_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 5, __PRIORITY__) #define EXTI_I2c_SetIntPriority(__PRIORITY__) SFR_DUAL_SET(IP2, IP2H, 6, __PRIORITY__) diff --git a/include/fw_hal.h b/include/fw_hal.h index 66046aa..4dd2a43 100644 --- a/include/fw_hal.h +++ b/include/fw_hal.h @@ -25,6 +25,7 @@ #include "fw_uart.h" #include "fw_adc.h" #include "fw_spi.h" +#include "fw_pwm.h" #include "fw_util.h" #endif diff --git a/include/fw_pwm.h b/include/fw_pwm.h new file mode 100644 index 0000000..f444979 --- /dev/null +++ b/include/fw_pwm.h @@ -0,0 +1,510 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef ___FW_PWM_H___ +#define ___FW_PWM_H___ + +#include "fw_conf.h" +#include "fw_types.h" + + +typedef enum +{ + PWM_Pin_1 = B00000001, + PWM_Pin_1N = B00000010, + PWM_Pin_2 = B00000100, + PWM_Pin_2N = B00001000, + PWM_Pin_3 = B00010000, + PWM_Pin_3N = B00100000, + PWM_Pin_4 = B01000000, + PWM_Pin_4N = B10000000, + PWMA_Pin_All = B11111111, + PWMB_Pin_All = B01010101, +} PWM_Pin_t; + +/** + * Trigger mode + * Side Mode: + * Depends on DIR + * Center Mode: counter increasing then decreasing + * CenterDown: trigger interrupt when meet target in decreasing + * CenterUp: trigger interrupt when meet target in increasing + * CenterBoth: trigger interrupt when meet target in both +*/ +typedef enum +{ + PWM_EdgeAlignment_Side = 0x00, + PWM_EdgeAlignment_CenterDown = 0x01, + PWM_EdgeAlignment_CenterUp = 0x10, + PWM_EdgeAlignment_CenterBoth = 0x11, +} PWM_EdgeAlignment_t; + +typedef enum +{ + PWM_CounterDirection_Up = 0x00, + PWM_CounterDirection_Down = 0x01, +} PWM_CounterDirection_t; + +/** + * Comparasion Output Mode: PWMx_CCRx vs PWMx_CNT => OCxREF +*/ +typedef enum +{ + PWM_OutputMode_NoAction = 0x00, // Fixed + PWM_OutputMode_TriggerHigh = 0x01, // OCxREF=1 when PWMA_CCR1=PWMA_CNT + PWM_OutputMode_TriggerLow = 0x02, // OCxREF=0 when PWMA_CCR1=PWMA_CNT + PWM_OutputMode_TriggerToggle = 0x03, // Toggle OCxREF when PWMA_CCR1=PWMA_CNT + PWM_OutputMode_AlwaysLow = 0x04, // OCxREF always low + PWM_OutputMode_AlwaysHigh = 0x05, // OCxREF always high + PWM_OutputMode_PWM_HighIfLess = 0x06, // OCxREF=1 when PWMA_CNT> 8)); \ + (PWMA_PSCRL = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) + +#define PWMA_SetAutoReloadPeriod(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMA_ARRH = ((__16BIT_VAL__) >> 8)); \ + (PWMA_ARRL = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) + +// PWMA all pins input/output OFF/ON +#define PWMA_SetOverallState(__STATE__) SFRX_ASSIGN(PWMA_BKR, 7, (__STATE__)) + +// PWMA Pins Output OFF/ON +#define PWMA_SetPinOutputState(__PINS__, __STATE__) do { \ + P_SW2 = 0x80; \ + PWMA_ENO = PWMA_ENO & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \ + P_SW2 = 0x00; \ + } while(0) +// Enable/Disable PWMB_BKR Control on Pins +#define PWMA_SetPinBrakeControl(__PINS__, __STATE__) do { \ + P_SW2 = 0x80; \ + PWMA_IOAUX = PWMA_IOAUX & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \ + P_SW2 = 0x00; \ + } while(0) +/** + * 0: New period will be written to [PWMA_ARRH,PWMA_ARRL] and take effect immediately + * 1: New period will be written to shadow register and loaded to [PWMA_ARRH,PWMA_ARRL] on next update event +*/ +#define PWMA_SetAutoReloadPeriodPreload(__STATE__) SFRX_ASSIGN(PWMA_CR1, 7, (__STATE__)) + +/** + * Turn off counter (call PWMA_SetCounterState()) before changing to different alignment +*/ +#define PWMA_SetEdgeAlignment(__ALIGN__) do{ \ + P_SW2 = 0x80;(PWMA_CR1 = PWMA_CR1 & ~(0x03 << 5) | ((__ALIGN__) << 5)); P_SW2 = 0x00; \ + }while(0) +/** + * 0: count from 0 to [PWMA_ARRH,PWMA_ARRL], then send an event and restart from 0 + * 1: count from [PWMA_ARRH,PWMA_ARRL] to 0, then send an event and restart from [PWMA_ARRH,PWMA_ARRL] +*/ +#define PWMA_SetCounterDirection(__DIR__) SFRX_ASSIGN(PWMA_CR1, 4, (__DIR__)) +/** + * 0: counter continues when update event occurs + * 1: counter stops(reset CEN) when update event occurs +*/ +#define PWMA_SetCounterOnePulse(__STATE__) SFRX_ASSIGN(PWMA_CR1, 3, (__STATE__)) +/** + * Work only when update events are enabled + * 0: An interrupt will be triggered by these events: counter overflow(upwards or downwards), soft set UG, timer/controller updates + * 1: An interrupt will be triggered(and set UIF=1) by counter overflow(upwards or downwards) +*/ +#define PWMA_SetUpdateEventSource(__STATE__) SFRX_ASSIGN(PWMA_CR1, 2, (__STATE__)) +/** + * 0:enable update events, 1:disable update events +*/ +#define PWMA_SetNonUpdateEvent(__STATE__) SFRX_ASSIGN(PWMA_CR1, 1, (__STATE__)) +/** + * 0:stop counter, 1:start counter +*/ +#define PWMA_SetCounterState(__STATE__) SFRX_ASSIGN(PWMA_CR1, 0, (__STATE__)) + +/** + * PWMA.1 - PWMA.4 io polar and on/off state +*/ +#define PWMA_PWM1_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 0, (__STATE__)) +#define PWMA_PWM1_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 1, (__POLAR__)) +#define PWMA_PWM1N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 2, (__STATE__)) +#define PWMA_PWM1N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 3, (__POLAR__)) + +#define PWMA_PWM2_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 4, (__STATE__)) +#define PWMA_PWM2_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 5, (__POLAR__)) +#define PWMA_PWM2N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER1, 6, (__STATE__)) +#define PWMA_PWM2N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER1, 7, (__POLAR__)) + +#define PWMA_PWM3_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 0, (__STATE__)) +#define PWMA_PWM3_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 1, (__POLAR__)) +#define PWMA_PWM3N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 2, (__STATE__)) +#define PWMA_PWM3N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 3, (__POLAR__)) + +#define PWMA_PWM4_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 4, (__STATE__)) +#define PWMA_PWM4_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 5, (__POLAR__)) +#define PWMA_PWM4N_SetPortState(__STATE__) SFRX_ASSIGN(PWMA_CCER2, 6, (__STATE__)) +#define PWMA_PWM4N_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMA_CCER2, 7, (__POLAR__)) + +/** + * Configurate PWMA.1 - PWMA.4 port direction +*/ +typedef enum +{ + PWMA_PortDirOut = 0x00, + PWMA_PortDirIn_TI1FP1_TI2FP2_TI3FP3_TI4FP4 = 0x01, + PWMA_PortDirIn_TI2FP1_TI1FP2_TI4FP3_TI3FP4 = 0x10, + PWMA_PortDirInTRC = 0x11, +} PWMA_PortDirection_t; +#define PWMA_PWM1_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR1 = PWMA_CCMR1 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM2_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR2 = PWMA_CCMR2 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM3_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR3 = PWMA_CCMR3 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM4_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR4 = PWMA_CCMR4 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) + +/** + * PWMA.1 - PWMA.4 comparison value preload OFF/ON + * 0: New values will be written to PWMx_CCRx and take effect immediately + * 1: New values will be written to shadow register and loaded to PWMx_CCRx on next update event +*/ +#define PWMA_PWM1_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR1, 3, (__STATE__)) +#define PWMA_PWM2_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR2, 3, (__STATE__)) +#define PWMA_PWM3_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR3, 3, (__STATE__)) +#define PWMA_PWM4_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMA_CCMR4, 3, (__STATE__)) + +/** + * Configurate PWMA.1 - PWMA.4 out mode +*/ +#define PWMA_PWM1_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR1 = PWMA_CCMR1 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM2_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR2 = PWMA_CCMR2 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM3_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR3 = PWMA_CCMR3 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM4_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMA_CCMR4 = PWMA_CCMR4 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) + +/** + * Configurate PWMA.1 - PWMA.4 capture/comparison value, this will affect duty cycle +*/ +#define PWMA_PWM1_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMA_CCR1H = ((__16BIT_VAL__) >> 8)); \ + (PWMA_CCR1L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM2_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMA_CCR2H = ((__16BIT_VAL__) >> 8)); \ + (PWMA_CCR2L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM3_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMA_CCR3H = ((__16BIT_VAL__) >> 8)); \ + (PWMA_CCR3L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM4_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMA_CCR4H = ((__16BIT_VAL__) >> 8)); \ + (PWMA_CCR4L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) + +/** + * PWM1 - PWM4 alternative ports +*/ +typedef enum +{ + // PWM1P PWM1N + PWMA_PWM1_AlterPort_P10_P11 = 0x00, + PWMA_PWM1_AlterPort_P20_P21 = 0x01, + PWMA_PWM1_AlterPort_P60_P61 = 0x10, +} PWMA_PWM1_AlterPort_t; + +typedef enum +{ + PWMA_PWM2_AlterPort_P12P54_P13 = 0x00, + PWMA_PWM2_AlterPort_P22_P23 = 0x01, + PWMA_PWM2_AlterPort_P62_P63 = 0x10, +} PWMA_PWM2_AlterPort_t; + +typedef enum +{ + PWMA_PWM3_AlterPort_P14_P15 = 0x00, + PWMA_PWM3_AlterPort_P24_P25 = 0x01, + PWMA_PWM3_AlterPort_P64_P65 = 0x10, +} PWMA_PWM3_AlterPort_t; + +typedef enum +{ + PWMA_PWM4_AlterPort_P16_P17 = 0x00, + PWMA_PWM4_AlterPort_P26_P27 = 0x01, + PWMA_PWM4_AlterPort_P66_P67 = 0x10, + PWMA_PWM4_AlterPort_P34_P33 = 0x11, +} PWMA_PWM4_AlterPort_t; + +// Alternative port selection +#define PWMA_PWM1_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMA_PS = PWMA_PS & ~(0x03 << 0) | ((__ALTER_PORT__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM2_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMA_PS = PWMA_PS & ~(0x03 << 2) | ((__ALTER_PORT__) << 2)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM3_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMA_PS = PWMA_PS & ~(0x03 << 4) | ((__ALTER_PORT__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMA_PWM4_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMA_PS = PWMA_PS & ~(0x03 << 6) | ((__ALTER_PORT__) << 6)); P_SW2 = 0x00; \ + }while(0) + + + +/**************************************************************************** / + * PWMB +*/ + +/** + * PWM clock prescaler + * + * side alignment: + * Fpwm = SYSCLK / (PWMx_PSCR + 1) / (PWMx_ARR + 1) + * central alignment: + * Fpwm = SYSCLK / (PWMx_PSCR + 1) / PWMx_ARR / 2 +*/ +#define PWMB_SetPrescaler(__16BIT_PRESCALER__) do { \ + P_SW2 = 0x80; \ + (PWMB_PSCRH = ((__16BIT_PRESCALER__) >> 8)); \ + (PWMB_PSCRL = ((__16BIT_PRESCALER__) & 0xFF)); \ + P_SW2 = 0x00; \ + } while(0) + +// PWMA all pins input/output OFF/ON +#define PWMB_SetOverallState(__STATE__) SFRX_ASSIGN(PWMB_BKR, 7, (__STATE__)) + +// Enable/Disable PWMB Pins Output +#define PWMB_SetPinOutputState(__PINS__, __STATE__) do { \ + P_SW2 = 0x80; \ + PWMB_ENO = PWMB_ENO & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \ + P_SW2 = 0x00; \ + } while(0) +// Enable/Disable PWMB_BKR Control on Pins +#define PWMB_SetPinBrakeControl(__PINS__, __STATE__) do { \ + P_SW2 = 0x80; \ + PWMB_IOAUX = PWMB_IOAUX & ~(__PINS__) | (((__STATE__) & 0x01)? (__PINS__) : 0x00); \ + P_SW2 = 0x00; \ + } while(0) + +/** + * 0:no preload, 1:enable auto preload +*/ +#define PWMB_SetAutoPreloadState(__STATE__) SFRX_ASSIGN(PWMB_CR1, 7, (__STATE__)) + +#define PWMB_SetEdgeAlignment(__ALIGN__) do{ \ + P_SW2 = 0x80; \ + (PWMB_CR1 = PWMB_CR1 & ~(0x03 << 5) | ((__ALIGN__) << 5)); \ + P_SW2 = 0x00; \ + }while(0) +/** + * 0: count upwards, 1: count downwards +*/ +#define PWMB_SetCounterDirection(__DIR__) SFRX_ASSIGN(PWMB_CR1, 4, (__DIR__)) +/** + * 0: counter continues when update event occurs + * 1: counter stops(reset CEN) when update event occurs +*/ +#define PWMB_SetCounterOnePulse(__STATE__) SFRX_ASSIGN(PWMB_CR1, 3, (__STATE__)) +/** + * Work only when update events are enabled + * 0: An interrupt will be triggered by these events: counter overflow(upwards or downwards), soft set UG, timer/controller updates + * 1: An interrupt will be triggered(and set UIF=1) by counter overflow(upwards or downwards) +*/ +#define PWMB_SetUpdateEventSource(__STATE__) SFRX_ASSIGN(PWMB_CR1, 2, (__STATE__)) +/** + * 0:enable update events, 1:disable update events +*/ +#define PWMB_SetNonUpdateEvent(__STATE__) SFRX_ASSIGN(PWMB_CR1, 1, (__STATE__)) +/** + * 0:disable counter, 1:enable counter +*/ +#define PWMB_SetCounterState(__STATE__) SFRX_ASSIGN(PWMB_CR1, 0, (__STATE__)) + + +/** + * PWMB.1(PWM5) - PWMB.4(PWM8) io polar and on/off state +*/ +#define PWMB_PWM1_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER1, 0, (__STATE__)) +#define PWMB_PWM1_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER1, 1, (__POLAR__)) + +#define PWMB_PWM2_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER1, 4, (__STATE__)) +#define PWMB_PWM2_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER1, 5, (__POLAR__)) + +#define PWMB_PWM3_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER2, 0, (__STATE__)) +#define PWMB_PWM3_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER2, 1, (__POLAR__)) + +#define PWMB_PWM4_SetPortState(__STATE__) SFRX_ASSIGN(PWMB_CCER2, 4, (__STATE__)) +#define PWMB_PWM4_SetPortPolar(__POLAR__) SFRX_ASSIGN(PWMB_CCER2, 5, (__POLAR__)) + +/** + * Configurate PWMB.1(PWM5) - PWMB.4(PWM8) port direction +*/ +typedef enum +{ + PWMB_PortDirOut = 0x00, + PWMB_PortDirIn_TI5FP5_TI6FP6_TI7FP7_TI8FP8 = 0x01, + PWMB_PortDirIn_TI6FP5_TI5FP6_TI8FP7_TI7FP8 = 0x10, + PWMB_PortDirInTRC = 0x11, +} PWMB_PortDirection_t; + +#define PWMB_PWM1_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR1 = PWMB_CCMR1 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM2_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR2 = PWMB_CCMR2 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM3_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR3 = PWMB_CCMR3 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM4_SetPortDirection(__PORT_DIR__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR4 = PWMB_CCMR4 & ~(0x03 << 0) | ((__PORT_DIR__) << 0)); P_SW2 = 0x00; \ + }while(0) + +/** + * PWMB.1 - PWMB.4 comparison value preload OFF/ON +*/ +#define PWMB_PWM1_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR1, 3, (__STATE__)) +#define PWMB_PWM2_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR2, 3, (__STATE__)) +#define PWMB_PWM3_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR3, 3, (__STATE__)) +#define PWMB_PWM4_SetComparePreload(__STATE__) SFRX_ASSIGN(PWMB_CCMR4, 3, (__STATE__)) + +/** + * Configurate PWMB.1(PWM5) - PWMB.4(PWM8) output mode +*/ +#define PWMB_PWM1_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR1 = PWMB_CCMR1 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM2_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR2 = PWMB_CCMR2 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM3_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR3 = PWMB_CCMR3 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM4_SetOutputMode(__MODE__) do{ \ + P_SW2 = 0x80;(PWMB_CCMR4 = PWMB_CCMR4 & ~(0x07 << 4) | ((__MODE__) << 4)); P_SW2 = 0x00; \ + }while(0) + +/** + * Configurate PWMB.1(PWM5) - PWMB.4(PWM8) capture/comparison value, this will affect duty cycle +*/ +#define PWMB_PWM1_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMB_CCR1H = ((__16BIT_VAL__) >> 8)); \ + (PWMB_CCR1L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM2_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMB_CCR2H = ((__16BIT_VAL__) >> 8)); \ + (PWMB_CCR2L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM3_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMB_CCR3H = ((__16BIT_VAL__) >> 8)); \ + (PWMB_CCR3L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM4_SetCaptureCompareValue(__16BIT_VAL__) do{ \ + P_SW2 = 0x80; \ + (PWMB_CCR4H = ((__16BIT_VAL__) >> 8)); \ + (PWMB_CCR4L = ((__16BIT_VAL__) & 0xFF)); \ + P_SW2 = 0x00; \ + }while(0) + +typedef enum +{ + PWMB_PWM5_AlterPort_P20 = 0x00, + PWMB_PWM5_AlterPort_P17 = 0x01, + PWMB_PWM5_AlterPort_P00 = 0x10, + PWMB_PWM5_AlterPort_P74 = 0x11, +} PWMB_PWM5_AlterPort_t; + +typedef enum +{ + PWMB_PWM6_AlterPort_P21 = 0x00, + PWMB_PWM6_AlterPort_P54 = 0x01, + PWMB_PWM6_AlterPort_P01 = 0x10, + PWMB_PWM6_AlterPort_P75 = 0x11, +} PWMB_PWM6_AlterPort_t; + +typedef enum +{ + PWMB_PWM7_AlterPort_P22 = 0x00, + PWMB_PWM7_AlterPort_P33 = 0x01, + PWMB_PWM7_AlterPort_P02 = 0x10, + PWMB_PWM7_AlterPort_P76 = 0x11, +} PWMB_PWM7_AlterPort_t; + +typedef enum +{ + PWMB_PWM8_AlterPort_P23 = 0x00, + PWMB_PWM8_AlterPort_P34 = 0x01, + PWMB_PWM8_AlterPort_P03 = 0x10, + PWMB_PWM8_AlterPort_P77 = 0x11, +} PWMB_PWM8_AlterPort_t; + +// Alternative port selection +#define PWMB_PWM1_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMB_PS = PWMB_PS & ~(0x03 << 0) | ((__ALTER_PORT__) << 0)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM2_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMB_PS = PWMB_PS & ~(0x03 << 2) | ((__ALTER_PORT__) << 2)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM3_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMB_PS = PWMB_PS & ~(0x03 << 4) | ((__ALTER_PORT__) << 4)); P_SW2 = 0x00; \ + }while(0) +#define PWMB_PWM4_SetPort(__ALTER_PORT__) do{ \ + P_SW2 = 0x80;(PWMB_PS = PWMB_PS & ~(0x03 << 6) | ((__ALTER_PORT__) << 6)); P_SW2 = 0x00; \ + }while(0) + + +#endif diff --git a/include/fw_reg_stc8h.h b/include/fw_reg_stc8h.h index f423a30..934a7bb 100644 --- a/include/fw_reg_stc8h.h +++ b/include/fw_reg_stc8h.h @@ -137,6 +137,10 @@ SFR(RSTCFG, 0xFF); #define TM4PS (*(unsigned char volatile __XDATA *)0xfea4) #define ADCTIM (*(unsigned char volatile __XDATA *)0xfea8) +/** + * suppress xdata space memory overlap + */ +/* #define PWM1_ETRPS (*(unsigned char volatile __XDATA *)0xfeb0) #define PWM1_ENO (*(unsigned char volatile __XDATA *)0xfeb1) #define PWM1_PS (*(unsigned char volatile __XDATA *)0xfeb2) @@ -223,11 +227,8 @@ SFR(RSTCFG, 0xFF); #define PWM2_BKR (*(unsigned char volatile __XDATA *)0xfefd) #define PWM2_DTR (*(unsigned char volatile __XDATA *)0xfefe) #define PWM2_OISR (*(unsigned char volatile __XDATA *)0xfeff) +*/ -/** - * suppress xdata space memory overlap - */ -/* #define PWMA_ETRPS (*(unsigned char volatile __XDATA *)0xfeb0) #define PWMA_ENO (*(unsigned char volatile __XDATA *)0xfeb1) #define PWMA_PS (*(unsigned char volatile __XDATA *)0xfeb2) @@ -244,6 +245,7 @@ SFR(RSTCFG, 0xFF); #define PWMA_SR1 (*(unsigned char volatile __XDATA *)0xfec5) #define PWMA_SR2 (*(unsigned char volatile __XDATA *)0xfec6) #define PWMA_EGR (*(unsigned char volatile __XDATA *)0xfec7) +#define PWMA_CCMRx 0xfec8 #define PWMA_CCMR1 (*(unsigned char volatile __XDATA *)0xfec8) #define PWMA_CCMR2 (*(unsigned char volatile __XDATA *)0xfec9) #define PWMA_CCMR3 (*(unsigned char volatile __XDATA *)0xfeca) @@ -283,6 +285,7 @@ SFR(RSTCFG, 0xFF); #define PWMB_SR1 (*(unsigned char volatile __XDATA *)0xfee5) #define PWMB_SR2 (*(unsigned char volatile __XDATA *)0xfee6) #define PWMB_EGR (*(unsigned char volatile __XDATA *)0xfee7) +#define PWMB_CCMRx 0xfee8 #define PWMB_CCMR1 (*(unsigned char volatile __XDATA *)0xfee8) #define PWMB_CCMR2 (*(unsigned char volatile __XDATA *)0xfee9) #define PWMB_CCMR3 (*(unsigned char volatile __XDATA *)0xfeea) @@ -314,7 +317,7 @@ SFR(RSTCFG, 0xFF); #define PWMB_BKR (*(unsigned char volatile __XDATA *)0xfefd) #define PWMB_DTR (*(unsigned char volatile __XDATA *)0xfefe) #define PWMB_OISR (*(unsigned char volatile __XDATA *)0xfeff) -*/ + ///////////////////////////////////////////////// //FD00H-FDFFH diff --git a/include/fw_spi.h b/include/fw_spi.h index 3491df1..2bee452 100644 --- a/include/fw_spi.h +++ b/include/fw_spi.h @@ -63,7 +63,7 @@ typedef enum /** * Alternative port selection */ -#define SPI_SwitchPort(__ALTER_PORT__) (P_SW1 = P_SW1 & ~(0x03 << 2) | ((__ALTER_PORT__) << 2)) +#define SPI_SetPort(__ALTER_PORT__) (P_SW1 = P_SW1 & ~(0x03 << 2) | ((__ALTER_PORT__) << 2)) uint8_t SPI_TxRx(uint8_t dat); diff --git a/include/fw_types.h b/include/fw_types.h index 64c0f38..2319697 100644 --- a/include/fw_types.h +++ b/include/fw_types.h @@ -63,6 +63,7 @@ typedef int32_t int64_t[2]; #define B11111100 0xFC #define B11111110 0xFE #define B11111111 0xFF +#define B01010101 0x55 typedef enum { diff --git a/include/fw_uart.h b/include/fw_uart.h index b12df68..edd64b3 100644 --- a/include/fw_uart.h +++ b/include/fw_uart.h @@ -65,11 +65,11 @@ typedef enum /** * Mode1: 8-bit UART, dynamic baud-rate, provided by Timer1 or Timer2 */ -void UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate); +void UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate); /** * Mode3: 9-bit UART, dynamic baud-rate, provided by Timer1 or Timer2 */ -void UART1_ConfigMode3Dyn9bitUart(UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate); +void UART1_ConfigMode3Dyn9bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate); void UART1_InterruptHandler(void); @@ -99,7 +99,7 @@ void UART1_TxString(uint8_t *str); /** * Dynamic baud-rate, provided by Timer2 */ -void UART2_Config(HAL_State_t freq1t, uint32_t baudrate); +void UART2_Config(HAL_State_t _1TMode, uint32_t baudrate); void UART2_TxChar(char dat); @@ -122,8 +122,8 @@ void UART2_TxString(uint8_t *str); /** * dynamic baud-rate from timer2 or timer3 */ -void UART3_ConfigOnTimer2(HAL_State_t freq1t, uint32_t baudrate); -void UART3_ConfigOnTimer3(HAL_State_t freq1t, uint32_t baudrate); +void UART3_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate); +void UART3_ConfigOnTimer3(HAL_State_t _1TMode, uint32_t baudrate); /**************************************************************************** / @@ -141,8 +141,8 @@ void UART3_ConfigOnTimer3(HAL_State_t freq1t, uint32_t baudrate); /** * dynamic baud-rate from timer2 or timer4 */ -void UART4_ConfigOnTimer2(HAL_State_t freq1t, uint32_t baudrate); -void UART4_ConfigOnTimer4(HAL_State_t freq1t, uint32_t baudrate); +void UART4_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate); +void UART4_ConfigOnTimer4(HAL_State_t _1TMode, uint32_t baudrate); #endif \ No newline at end of file diff --git a/src/fw_uart.c b/src/fw_uart.c index df0e4bc..ceb81a6 100644 --- a/src/fw_uart.c +++ b/src/fw_uart.c @@ -25,11 +25,11 @@ __bit busy; * UART1 */ -int16_t _UART1_Timer_InitValueCalculate(HAL_State_t freq1t, uint32_t baudrate) +int16_t _UART1_Timer_InitValueCalculate(HAL_State_t _1TMode, uint32_t baudrate) { uint32_t value, sysclk = SYS_GetSysClock(); value = sysclk / (4 * baudrate); - if (!freq1t) + if (!_1TMode) value = value / 12; if (value > 0xFFFF) return 0; @@ -37,14 +37,14 @@ int16_t _UART1_Timer_InitValueCalculate(HAL_State_t freq1t, uint32_t baudrate) return 0xFFFF - value + 1; } -void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate) +void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate) { - uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate); + uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); UART1_SetBaudSource(baudSource); // Timer1 configuration. Mode0 only, mode2 is covered by mode0 so it is unnecessary. if (baudSource == UART1_BaudSource_Timer1) { - TIM_Timer1_Set1TMode(freq1t); + TIM_Timer1_Set1TMode(_1TMode); TIM_Timer1_SetMode(TIM_TimerMode_16BitAuto); TIM_Timer1_SetInitValue(init >> 8, init & 0xFF); TIM_Timer1_SetRunState(HAL_State_ON); @@ -53,21 +53,21 @@ void _UART1_ConfigDynUart(UART1_BaudSource_t baudSource, HAL_State_t freq1t, uin else { // Timer2: 1T mode and initial value. prescaler is ignored, no interrupt. - TIM_Timer2_Set1TMode(freq1t); + TIM_Timer2_Set1TMode(_1TMode); TIM_Timer2_SetInitValue(init >> 8, init & 0xFF); TIM_Timer2_SetRunState(HAL_State_ON); } } -void UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate) +void UART1_ConfigMode1Dyn8bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate) { SM0=0; SM1=1; - _UART1_ConfigDynUart(baudSource, freq1t, baudrate); + _UART1_ConfigDynUart(baudSource, _1TMode, baudrate); } -void UART1_ConfigMode3Dyn9bitUart(UART1_BaudSource_t baudSource, HAL_State_t freq1t, uint32_t baudrate) +void UART1_ConfigMode3Dyn9bitUart(UART1_BaudSource_t baudSource, HAL_State_t _1TMode, uint32_t baudrate) { SM0=1; SM1=1; - _UART1_ConfigDynUart(baudSource, freq1t, baudrate); + _UART1_ConfigDynUart(baudSource, _1TMode, baudrate); } void UART1_InterruptHandler(void) @@ -126,11 +126,11 @@ void UART1_TxString(uint8_t *str) * UART2 */ -void UART2_Config(HAL_State_t freq1t, uint32_t baudrate) +void UART2_Config(HAL_State_t _1TMode, uint32_t baudrate) { - uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate); + uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); // Timer2: 1T mode and initial value. prescaler is ignored, no interrupt. - TIM_Timer2_Set1TMode(freq1t); + TIM_Timer2_Set1TMode(_1TMode); TIM_Timer2_SetInitValue(init >> 8, init & 0xFF); TIM_Timer2_SetRunState(HAL_State_ON); } @@ -158,22 +158,22 @@ void UART2_TxString(uint8_t *str) * UART3 */ -void UART3_ConfigOnTimer2(HAL_State_t freq1t, uint32_t baudrate) +void UART3_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate) { UART3_SetBaudSource(0x00); - uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate); + uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); // Timer2: 1T mode and initial value. prescaler is ignored, no interrupt. - TIM_Timer2_Set1TMode(freq1t); + TIM_Timer2_Set1TMode(_1TMode); TIM_Timer2_SetInitValue(init >> 8, init & 0xFF); TIM_Timer2_SetRunState(HAL_State_ON); } -void UART3_ConfigOnTimer3(HAL_State_t freq1t, uint32_t baudrate) +void UART3_ConfigOnTimer3(HAL_State_t _1TMode, uint32_t baudrate) { UART3_SetBaudSource(0x01); - uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate); + uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); // Timer3: 1T mode and initial value. prescaler is ignored, no interrupt. - TIM_Timer3_Set1TMode(freq1t); + TIM_Timer3_Set1TMode(_1TMode); TIM_Timer3_SetInitValue(init >> 8, init & 0xFF); TIM_Timer3_SetRunState(HAL_State_ON); } @@ -183,20 +183,20 @@ void UART3_ConfigOnTimer3(HAL_State_t freq1t, uint32_t baudrate) * UART4 */ -void UART4_ConfigOnTimer2(HAL_State_t freq1t, uint32_t baudrate) +void UART4_ConfigOnTimer2(HAL_State_t _1TMode, uint32_t baudrate) { UART4_SetBaudSource(0x00); - uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate); - TIM_Timer2_Set1TMode(freq1t); + uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); + TIM_Timer2_Set1TMode(_1TMode); TIM_Timer2_SetInitValue(init >> 8, init & 0xFF); TIM_Timer2_SetRunState(HAL_State_ON); } -void UART4_ConfigOnTimer4(HAL_State_t freq1t, uint32_t baudrate) +void UART4_ConfigOnTimer4(HAL_State_t _1TMode, uint32_t baudrate) { UART4_SetBaudSource(0x01); - uint16_t init = _UART1_Timer_InitValueCalculate(freq1t, baudrate); - TIM_Timer4_Set1TMode(freq1t); + uint16_t init = _UART1_Timer_InitValueCalculate(_1TMode, baudrate); + TIM_Timer4_Set1TMode(_1TMode); TIM_Timer4_SetInitValue(init >> 8, init & 0xFF); TIM_Timer4_SetRunState(HAL_State_ON); }