feat: eeprom iap operations
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IOsetting
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591a15de2c
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c9eec37a2b
108
demo/iap/eeprom_iap.c
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108
demo/iap/eeprom_iap.c
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// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/***
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* Demo: EEPROM IAP read, write, erase and software reset
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*/
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#include "fw_hal.h"
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#define TEST_ADDR 0x0400
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#define TEST_SIZE 32
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void TestIAPRead(uint16_t addr, uint8_t size)
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{
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uint8_t pos = 0;
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UART1_TxString("IAP_CmdRead: ");
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for (pos = 0; pos < size; pos++)
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{
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IAP_CmdRead(addr + pos);
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if (IAP_IsCmdFailed())
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{
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UART1_TxString("__ ");
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IAP_ClearCmdFailFlag();
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}
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else
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{
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UART1_TxHex(IAP_ReadData());
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UART1_TxChar(' ');
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}
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}
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UART1_TxString("\r\n");
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}
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void TestIAPWrite(uint16_t addr, uint8_t size)
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{
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uint8_t pos = 0;
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UART1_TxString("IAP_CmdWrite: ");
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for (pos = 0; pos < size; pos++)
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{
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IAP_WriteData(pos);
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IAP_CmdWrite(addr + pos);
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if (IAP_IsCmdFailed())
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{
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UART1_TxString("__ ");
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IAP_ClearCmdFailFlag();
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}
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else
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{
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UART1_TxHex(pos);
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UART1_TxChar(' ');
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}
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}
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UART1_TxString("\r\n");
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}
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void TestIAPErase(uint16_t addr)
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{
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uint8_t pos = 0;
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UART1_TxString("IAP_CmdErase: ");
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IAP_CmdErase(addr);
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if (IAP_IsCmdFailed())
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{
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UART1_TxString("failed.\r\n");
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IAP_ClearCmdFailFlag();
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}
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else
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{
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UART1_TxString("succeeded.\r\n");
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}
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}
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int main(void)
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{
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SYS_SetClock();
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UART1_Config8bitUart(UART1_BaudSource_Timer2, HAL_State_ON, 115200);
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UART1_TxString("Test restarted\r\n");
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IAP_SetWaitTime();
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IAP_SetEnabled(HAL_State_ON);
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TestIAPRead(TEST_ADDR, TEST_SIZE);
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SYS_Delay(500);
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TestIAPWrite(TEST_ADDR, TEST_SIZE);
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SYS_Delay(500);
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TestIAPRead(TEST_ADDR, TEST_SIZE);
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SYS_Delay(500);
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TestIAPErase(TEST_ADDR);
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SYS_Delay(500);
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TestIAPRead(TEST_ADDR, TEST_SIZE);
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IAP_SetEnabled(HAL_State_OFF);
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SYS_Delay(2000);
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UART1_TxString("Software reset\r\n");
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SYS_Delay(1000);
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IAP_SoftReset();
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return 0;
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}
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@ -26,6 +26,7 @@
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#include "fw_adc.h"
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#include "fw_i2c.h"
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#include "fw_spi.h"
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#include "fw_iap.h"
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#include "fw_util.h"
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#if (__CONF_MCU_TYPE == 2 )
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106
include/fw_iap.h
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include/fw_iap.h
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// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ___FW_IAP_H___
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#define ___FW_IAP_H___
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#include "fw_conf.h"
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#include "fw_types.h"
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/**
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* EEPROM size and IAP address of different series
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*
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* | LINE | SIZE | ADDR START | ADDR END |
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* | --------- | --- | ----- | ----- |
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* | STC8H1K08 | 4K | 0x0000 | 0x0FFF |
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* | STC8H1K24 | 4K | 0x0000 | 0x0FFF |
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* | STC8H3K60S2 | 4K | 0x0000 | 0x0FFF |
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* | STC8H3K60S4 | 4K | 0x0000 | 0x0FFF |
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* | STC8H8K60U | 4K | 0x0000 | 0x0FFF |
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* | STC8H1K16 | 12K | 0x0000 | 0x2FFF |
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* | STC8H3K48S2 | 16K | 0x0000 | 0x3FFF |
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* | STC8H3K48S4 | 16K | 0x0000 | 0x3FFF |
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* | STC8H8K48U | 16K | 0x0000 | 0x3FFF |
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* | STC8H3K32S2 | 32K | 0x0000 | 0x7FFF |
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* | STC8H3K32S4 | 32K | 0x0000 | 0x7FFF |
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* | STC8H8K32U | 32K | 0x0000 | 0x7FFF |
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*
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*/
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typedef enum
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{
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IAP_RestartFrom_UserCode = 0x00,
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IAP_RestartFrom_ISPCode = 0x01,
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} IAP_RestartFrom_t;
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#define IAP_SetWaitTime() (IAP_TPS = (uint8_t)(__CONF_FOSC / 1000000UL))
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#define IAP_ReadData() (IAP_DATA)
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#define IAP_WriteData(__BYTE__) (IAP_DATA = (__BYTE__))
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/**
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* Set cmd to idle
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*/
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#define IAP_SetIdle() (IAP_CMD = IAP_CMD & ~(0x03))
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/**
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* Read one byte
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*/
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#define IAP_CmdRead(__16BIT_ADDR__) do{ \
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EA = 0; \
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IAP_ADDRH = ((__16BIT_ADDR__) >> 8); \
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IAP_ADDRL = ((__16BIT_ADDR__) & 0xFF); \
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IAP_CMD = IAP_CMD & ~(0x03) | 0x01; \
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IAP_TRIG = 0x5A; \
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IAP_TRIG = 0xA5; \
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NOP();NOP(); \
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IAP_SetIdle(); \
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EA = 1; \
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}while(0)
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/**
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* Write one byte, 1->0 only
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*/
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#define IAP_CmdWrite(__16BIT_ADDR__) do{ \
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EA = 0; \
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IAP_ADDRH = ((__16BIT_ADDR__) >> 8); \
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IAP_ADDRL = ((__16BIT_ADDR__) & 0xFF); \
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IAP_CMD = IAP_CMD & ~(0x03) | 0x02; \
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IAP_TRIG = 0x5A; \
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IAP_TRIG = 0xA5; \
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NOP();NOP(); \
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IAP_SetIdle(); \
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EA = 1; \
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}while(0)
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/**
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* Erase one section (512 bytes), set all bytes to 0xFF
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*/
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#define IAP_CmdErase(__16BIT_ADDR__) do{ \
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EA = 0; \
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IAP_ADDRH = ((__16BIT_ADDR__) >> 8); \
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IAP_ADDRL = ((__16BIT_ADDR__) & 0xFF); \
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IAP_CMD = IAP_CMD & ~(0x03) | 0x03; \
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IAP_TRIG = 0x5A; \
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IAP_TRIG = 0xA5; \
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NOP();NOP(); \
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IAP_SetIdle(); \
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EA = 1; \
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}while(0)
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#define IAP_SetEnabled(__STATE__) SFR_ASSIGN(IAP_CONTR, 7, __STATE__)
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#define IAP_SetRestartFrom(__FROM__) SFR_ASSIGN(IAP_CONTR, 6, __FROM__)
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#define IAP_SoftReset() SFR_SET(IAP_CONTR, 5)
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#define IAP_IsCmdFailed() (IAP_CONTR & (0x01 << 4))
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#define IAP_ClearCmdFailFlag() SFR_RESET(IAP_CONTR, 4)
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#endif
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