From c786635e3318a6d8efa496c444de8828fb033580 Mon Sep 17 00:00:00 2001 From: IOsetting Date: Mon, 10 Jan 2022 17:03:03 +0800 Subject: [PATCH] feat: analog comparator --- include/fw_cmp.h | 136 ++++++++++++++++++++++++++++++++++++++++++++++ include/fw_exti.h | 6 +- include/fw_iap.h | 39 ++++++++----- include/fw_wdt.h | 2 +- 4 files changed, 164 insertions(+), 19 deletions(-) create mode 100644 include/fw_cmp.h diff --git a/include/fw_cmp.h b/include/fw_cmp.h new file mode 100644 index 0000000..d020671 --- /dev/null +++ b/include/fw_cmp.h @@ -0,0 +1,136 @@ +// Copyright 2021 IOsetting +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef ___FW_CMP_H___ +#define ___FW_CMP_H___ + +#include "fw_conf.h" +#include "fw_types.h" + +/** + * STC8 MCU analog comparator + * + * 2P: 2 positive input options + * 4P: 4 positive input options + * + * | | 2P+2N | 4P+2N | + * | STC8G1K08 | Y | | + * | STC8G1K08-8Pin | N | | + * | STC8G1K08A | N | | + * | STC8G2K64S4 | Y | | + * | STC8G2K64S2 | Y | | + * | STC8G1K08T | Y | | + * | STC15H2K64S4 | Y | | + * | STC8H1K08 | Y | | + * | STC8H1K28 | Y | | + * | STC8H3K64S4 | Y | | + * | STC8H3K64S2 | Y | | + * | STC8H2K64T | Y | | + * | STC8H8K64U | | Y | + * | STC8H4K64TLR | | Y | + * | STC8H4K64TLCD | | Y | + * | STC8H4K64LCD | | Y | +*/ + +typedef enum +{ + CMP_OLD_PositiveInput_P37 = 0x00, + CMP_OLD_PositiveInput_ADC = 0x01, +} CMP_OLD_PositiveInput_t; + +typedef enum +{ + CMP_OLD_NegativeInput_RefV = 0x00, + CMP_OLD_NegativeInput_P36 = 0x01, +} CMP_OLD_NegativeInput_t; + +typedef enum +{ + CMP_PositiveInput_P37 = 0x00, + CMP_PositiveInput_P50 = 0x01, + CMP_PositiveInput_P51 = 0x02, + CMP_PositiveInput_ADC = 0x03, +} CMP_PositiveInput_t; + +typedef enum +{ + CMP_NegativeInput_P36 = 0x00, + CMP_NegativeInput_RefV = 0x01, +} CMP_NegativeInput_t; + +typedef enum +{ + CMP_Hysteresis_0mV = 0x00, + CMP_Hysteresis_10mV = 0x01, + CMP_Hysteresis_20mV = 0x02, + CMP_Hysteresis_30mV = 0x03, +} CMP_Hysteresis_t; + +#define CMP_SetEnabled(__STATE__) SFR_ASSIGN(CMPCR1, 7, __STATE__) +#define CMP_ClearInterrupt() SFR_ASSIGN(CMPCR1, 6) +/** + * for 2P+2N series. + * Set positive input pin, 0:P36, 1:ADC +*/ +#define CMP_OLD_SetPositiveInput(__INPUT__) SFR_ASSIGN(CMPCR1, 3, __INPUT__) +/** + * for 4P+2N series. + * Set positive input pin, 0:P36, 1:P50, 2:P51, 3:ADC +*/ +#define CMP_SetPositiveInput(__INPUT__) do{ \ + SFRX_ON(); \ + CMPEXCFG = CMPEXCFG & ~(0x03) | (__INPUT__ & 0x03); \ + SFRX_OFF(); \ + } while(0) +/** + * for 2P+2N series. + * Set negative input pin, 0:1.19V ref, 1:P36 +*/ +#define CMP_OLD_SetNegativeInput(__INPUT__) SFR_ASSIGN(CMPCR1, 2, __INPUT__) +/** + * for 4P+2N series. + * Set negative input pin, 0:P36, 1:1.19Vref +*/ +#define CMP_SetNegativeInput(__INPUT__) SFRX_ASSIGN(CMPEXCFG, 2, __INPUT__) + +/** + * Result output + * 0:no output, 1:output to P34 or P41 +*/ +#define CMP_SetResultOutputState(__STATE__) SFR_ASSIGN(CMPCR1, 1, __STATE__) +#define CMP_ReadResultOutput() (CMPCR1 & 0x01) +/** + * 0: P34/P41 output high when result is 1 + * 1: P34/P41 output low when result is 1 +*/ +#define CMP_SetResultOutputInvert(__STATE__) SFR_ASSIGN(CMPCR2, 7, __STATE__) +/** + * 0: Enable 0.1us analog filter + * 1: Disable 0.1us analog filter +*/ +#define CMP_SetFilterDisabled(__STATE__) SFR_ASSIGN(CMPCR2, 6, __STATE__) +/** + * Comparator result will be delayed for (__CLOCKS__ + 2) clocks +*/ +#define CMP_SetDebouncingClocks(__CLOCKS__) CMPCR2 = CMPCR2 & ~(0x3F) | (__CLOCKS__ & 0x3F) +/** + * Set comparator hysteresis for producing stable switching behavior. +*/ +#define CMP_SetHysteresis(__HYST__) do{ \ + SFRX_ON(); \ + CMPEXCFG = CMPEXCFG & ~(0x03 << 6) | (__HYST__ << 6); \ + SFRX_OFF(); \ + } while(0) + +#endif diff --git a/include/fw_exti.h b/include/fw_exti.h index f482dea..78b2151 100644 --- a/include/fw_exti.h +++ b/include/fw_exti.h @@ -126,10 +126,8 @@ typedef enum #define EXTI_Int3_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 5, __STATE__) #define EXTI_Int2_SetIntState(__STATE__) SFR_ASSIGN(INTCLKO, 4, __STATE__) -#define EXTI_INT_CompRise_ON SFR_SET(CMPCR1, 5) -#define EXTI_INT_CompRise_OFF SFR_RESET(CMPCR1, 5) -#define EXTI_INT_CompFall_ON SFR_SET(CMPCR1, 4) -#define EXTI_INT_CompFall_OFF SFR_RESET(CMPCR1, 4) +#define EXTI_CMP_SetRiseIntState(__STATE__) SFR_ASSIGN(CMPCR1, 5, __STATE__) +#define EXTI_CMP_SetFallIntState(__STATE__) SFR_ASSIGN(CMPCR1, 4, __STATE__) #define EXTI_I2C_SetMstIntState(__STATE__) SFRX_ASSIGN(I2CMSCR, 7, __STATE__) #define EXTI_I2C_SetSlvStartIntState(__STATE__) SFRX_ASSIGN(I2CSLCR, 6, __STATE__) diff --git a/include/fw_iap.h b/include/fw_iap.h index 902d9cd..e7b5197 100644 --- a/include/fw_iap.h +++ b/include/fw_iap.h @@ -21,20 +21,31 @@ /** * EEPROM size and IAP address of different series * - * | LINE | SIZE | ADDR START | ADDR END | - * | --------- | --- | ----- | ----- | - * | STC8H1K08 | 4K | 0x0000 | 0x0FFF | - * | STC8H1K24 | 4K | 0x0000 | 0x0FFF | - * | STC8H3K60S2 | 4K | 0x0000 | 0x0FFF | - * | STC8H3K60S4 | 4K | 0x0000 | 0x0FFF | - * | STC8H8K60U | 4K | 0x0000 | 0x0FFF | - * | STC8H1K16 | 12K | 0x0000 | 0x2FFF | - * | STC8H3K48S2 | 16K | 0x0000 | 0x3FFF | - * | STC8H3K48S4 | 16K | 0x0000 | 0x3FFF | - * | STC8H8K48U | 16K | 0x0000 | 0x3FFF | - * | STC8H3K32S2 | 32K | 0x0000 | 0x7FFF | - * | STC8H3K32S4 | 32K | 0x0000 | 0x7FFF | - * | STC8H8K32U | 32K | 0x0000 | 0x7FFF | + * | LINE | SIZE | ADDR START | ADDR END | + * | --------- | --- | ----- | ----- | + * | STC8G1K08 | 4K | 0x0000 | 0x0FFF | + * | STC8G1K08-8Pin | 4K | 0x0000 | 0x0FFF | + * | STC8G1K08A | 4K | 0x0000 | 0x0FFF | + * | STC8G1K08T | 4K | 0x0000 | 0x0FFF | + * | STC8G2K60S4 | 4K | 0x0000 | 0x0FFF | + * | STC8G2K60S2 | 4K | 0x0000 | 0x0FFF | + * | STC8H1K08 | 4K | 0x0000 | 0x0FFF | + * | STC8H1K24 | 4K | 0x0000 | 0x0FFF | + * | STC8H3K60S2 | 4K | 0x0000 | 0x0FFF | + * | STC8H3K60S4 | 4K | 0x0000 | 0x0FFF | + * | STC8H8K60U | 4K | 0x0000 | 0x0FFF | + * | STC8G1K04 | 8K | 0x0000 | 0x1FFF | + * | STC8H1K16 | 12K | 0x0000 | 0x2FFF | + * | STC8H3K48S2 | 16K | 0x0000 | 0x3FFF | + * | STC8H3K48S4 | 16K | 0x0000 | 0x3FFF | + * | STC8H8K48U | 16K | 0x0000 | 0x3FFF | + * | STC8G2K48S4 | 16K | 0x0000 | 0x3FFF | + * | STC8G2K48S2 | 16K | 0x0000 | 0x3FFF | + * | STC8H3K32S2 | 32K | 0x0000 | 0x7FFF | + * | STC8H3K32S4 | 32K | 0x0000 | 0x7FFF | + * | STC8H8K32U | 32K | 0x0000 | 0x7FFF | + * | STC8G2K32S4 | 32K | 0x0000 | 0x7FFF | + * | STC8G2K32S2 | 32K | 0x0000 | 0x7FFF | * */ diff --git a/include/fw_wdt.h b/include/fw_wdt.h index 2843343..9aebd0d 100644 --- a/include/fw_wdt.h +++ b/include/fw_wdt.h @@ -19,7 +19,7 @@ #include "fw_types.h" /******************************************************** - * STC8 watchdog reset behavior is different from STC15 + * STC8 watchdog behavior is different from STC15 * * STC8 watchdog will ALWAYS reset chip from ISP code region inspite of the * setting of SWBS in IAP_CONTR