159 lines
6.6 KiB
C
159 lines
6.6 KiB
C
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// Copyright 2021 IOsetting <iosetting(at)outlook.com>
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __FW_MPU6050__
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#define __FW_MPU6050__
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#include "fw_hal.h"
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#define MPU6050_ADDR 0xD0 // MPU6050 address for write
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/**
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* Register Address
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*/
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#define MPU6050_REG_SELF_TEST_X 0x0D // RW
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#define MPU6050_REG_SELF_TEST_Y 0x0E // RW
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#define MPU6050_REG_SELF_TEST_Z 0x0F // RW
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#define MPU6050_REG_SELF_TEST_A 0x10 // RW
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#define MPU6050_REG_SMPLRT_DIV 0x19 // RW, Sample Rate Divider
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#define MPU6050_REG_CONFIG 0x1A // RW, Configuration
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#define MPU6050_REG_GYRO_CONFIG 0x1B // RW, Gyroscope Configuration
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#define MPU6050_REG_ACCEL_CONFIG 0x1C // RW, Accelerometer Configuration
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#define MPU6050_REG_FIFO_EN 0x23 // RW
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#define MPU6050_REG_I2C_MST_CTRL 0x24 // RW
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#define MPU6050_REG_I2C_SLV0_ADDR 0x25 // RW
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#define MPU6050_REG_I2C_SLV0_REG 0x26 // RW
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#define MPU6050_REG_I2C_SLV0_CTRL 0x27 // RW
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#define MPU6050_REG_I2C_SLV1_ADDR 0x28 // RW
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#define MPU6050_REG_I2C_SLV1_REG 0x29 // RW
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#define MPU6050_REG_I2C_SLV1_CTRL 0x2A // RW
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#define MPU6050_REG_I2C_SLV2_ADDR 0x2B // RW
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#define MPU6050_REG_I2C_SLV2_REG 0x2C // RW
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#define MPU6050_REG_I2C_SLV2_CTRL 0x2D // RW
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#define MPU6050_REG_I2C_SLV3_ADDR 0x2E // RW
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#define MPU6050_REG_I2C_SLV3_REG 0x2F // RW
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#define MPU6050_REG_I2C_SLV3_CTRL 0x30 // RW
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#define MPU6050_REG_I2C_SLV4_ADDR 0x31 // RW
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#define MPU6050_REG_I2C_SLV4_REG 0x32 // RW
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#define MPU6050_REG_I2C_SLV4_DO 0x33 // RW
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#define MPU6050_REG_I2C_SLV4_CTRL 0x34 // RW
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#define MPU6050_REG_I2C_SLV4_DI 0x35 // R
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#define MPU6050_REG_I2C_MST_STATUS 0x36 // R
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#define MPU6050_REG_INT_PIN_CFG 0x37 // RW
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#define MPU6050_REG_INT_ENABLE 0x38 // RW
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#define MPU6050_REG_INT_STATUS 0x3A // R
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#define MPU6050_REG_ACCEL_XOUT_H 0x3B // R
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#define MPU6050_REG_ACCEL_XOUT_L 0x3C // R
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#define MPU6050_REG_ACCEL_YOUT_H 0x3D // R
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#define MPU6050_REG_ACCEL_YOUT_L 0x3E // R
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#define MPU6050_REG_ACCEL_ZOUT_H 0x3F // R
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#define MPU6050_REG_ACCEL_ZOUT_L 0x40 // R
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#define MPU6050_REG_TEMP_OUT_H 0x41 // R
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#define MPU6050_REG_TEMP_OUT_L 0x42 // R
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#define MPU6050_REG_GYRO_XOUT_H 0x43 // R
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#define MPU6050_REG_GYRO_XOUT_L 0x44 // R
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#define MPU6050_REG_GYRO_YOUT_H 0x45 // R
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#define MPU6050_REG_GYRO_YOUT_L 0x46 // R
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#define MPU6050_REG_GYRO_ZOUT_H 0x47 // R
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#define MPU6050_REG_GYRO_ZOUT_L 0x48 // R
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#define MPU6050_REG_EXT_SENS_DATA_00 0x49 // R
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#define MPU6050_REG_EXT_SENS_DATA_01 0x4A // R
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#define MPU6050_REG_EXT_SENS_DATA_02 0x4B // R
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#define MPU6050_REG_EXT_SENS_DATA_03 0x4C // R
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#define MPU6050_REG_EXT_SENS_DATA_04 0x4D // R
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#define MPU6050_REG_EXT_SENS_DATA_05 0x4E // R
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#define MPU6050_REG_EXT_SENS_DATA_06 0x4F // R
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#define MPU6050_REG_EXT_SENS_DATA_07 0x50 // R
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#define MPU6050_REG_EXT_SENS_DATA_08 0x51 // R
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#define MPU6050_REG_EXT_SENS_DATA_09 0x52 // R
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#define MPU6050_REG_EXT_SENS_DATA_10 0x53 // R
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#define MPU6050_REG_EXT_SENS_DATA_11 0x54 // R
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#define MPU6050_REG_EXT_SENS_DATA_12 0x55 // R
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#define MPU6050_REG_EXT_SENS_DATA_13 0x56 // R
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#define MPU6050_REG_EXT_SENS_DATA_14 0x57 // R
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#define MPU6050_REG_EXT_SENS_DATA_15 0x58 // R
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#define MPU6050_REG_EXT_SENS_DATA_16 0x59 // R
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#define MPU6050_REG_EXT_SENS_DATA_17 0x5A // R
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#define MPU6050_REG_EXT_SENS_DATA_18 0x5B // R
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#define MPU6050_REG_EXT_SENS_DATA_19 0x5C // R
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#define MPU6050_REG_EXT_SENS_DATA_20 0x5D // R
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#define MPU6050_REG_EXT_SENS_DATA_21 0x5E // R
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#define MPU6050_REG_EXT_SENS_DATA_22 0x5F // R
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#define MPU6050_REG_EXT_SENS_DATA_23 0x60 // R
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#define MPU6050_REG_I2C_SLV0_DO 0x63 // RW
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#define MPU6050_REG_I2C_SLV1_DO 0x64 // RW
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#define MPU6050_REG_I2C_SLV2_DO 0x65 // RW
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#define MPU6050_REG_I2C_SLV3_DO 0x66 // RW
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#define MPU6050_REG_I2C_MST_DELAY_CTRL 0x67 // RW
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#define MPU6050_REG_SIGNAL_PATH_RESET 0x68 // RW
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#define MPU6050_REG_USER_CTRL 0x6A // RW
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#define MPU6050_REG_PWR_MGMT_1 0x6B // RW
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#define MPU6050_REG_PWR_MGMT_2 0x6C // RW
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#define MPU6050_REG_FIFO_COUNTH 0x72 // RW
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#define MPU6050_REG_FIFO_COUNTL 0x73 // RW
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#define MPU6050_REG_FIFO_R_W 0x74 // RW
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#define MPU6050_REG_WHO_AM_I 0x75 // R #define
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typedef enum
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{
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MPU6050_Wakeup_Freq_1p25Hz = 0x00,
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MPU6050_Wakeup_Freq_5Hz = 0x01,
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MPU6050_Wakeup_Freq_20Hz = 0x02,
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MPU6050_Wakeup_Freq_40Hz = 0x03,
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} MPU6050_Wakeup_Freq_t;
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typedef enum
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{
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MPU6050_DLPF_Delay0ms = 0x00,
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MPU6050_DLPF_Delay2ms = 0x01,
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MPU6050_DLPF_Delay3ms = 0x02,
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MPU6050_DLPF_Delay5ms = 0x03,
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MPU6050_DLPF_Delay8ms = 0x04,
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MPU6050_DLPF_Delay13ms = 0x05,
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MPU6050_DLPF_Delay19ms = 0x06,
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} MPU6050_DLPF_t;
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typedef enum
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{
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MPU6050_Gyro_FullScaleRange_250dps = 0x00,
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MPU6050_Gyro_FullScaleRange_500dps = 0x01,
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MPU6050_Gyro_FullScaleRange_1000dps = 0x02,
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MPU6050_Gyro_FullScaleRange_2000dps = 0x03,
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} MPU6050_Gyro_FullScaleRange_t;
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typedef enum
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{
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MPU6050_Acc_FullScaleRange_2g = 0x00,
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MPU6050_Acc_FullScaleRange_4g = 0x01,
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MPU6050_Acc_FullScaleRange_8g = 0x02,
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MPU6050_Acc_FullScaleRange_16g = 0x03,
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} MPU6050_Acc_FullScaleRange_t;
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uint8_t MPU6050_Read(uint8_t addr);
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uint16_t MPU6050_ReadInt(uint8_t addr);
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void MPU6050_ReadAll(uint16_t *buf);
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void MPU6050_Init(void);
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void MPU6050_Reset(void);
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void MPU6050_EnterSleepMode(void);
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void MPU6050_DisableTemperature(HAL_State_t state);
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void MPU6050_EnableLowPowerMode(MPU6050_Wakeup_Freq_t freq);
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void MPU6050_DisableLowPowerMode(void);
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void MPU6050_SetSampleRateDiv(uint8_t div);
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void MPU6050_SetDLPF(MPU6050_DLPF_t filter);
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void MPU6050_SetGyroFullScaleRange(MPU6050_Gyro_FullScaleRange_t range);
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void MPU6050_SetAccFullScaleRange(MPU6050_Acc_FullScaleRange_t range);
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#endif // __FW_MPU6050__
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