//sfr CHIP_ID = 0xA1; // ReadOnly: reading chip ID
#define CHIP_ID SAFE_MOD
sfrGLOBAL_CFG=0xB1;// global config, Write@SafeMode
#define bBOOT_LOAD 0x20 // ReadOnly: boot loader status for discriminating BootLoader or Application: set 1 by power on reset, clear 0 by software reset
#define bSW_RESET 0x10 // software reset bit, auto clear by hardware
#define bCODE_WE 0x08 // enable flash-ROM (include code & Data-Flash) being program or erasing: 0=writing protect, 1=enable program and erase
#define bDATA_WE 0x04 // enable Data-Flash (flash-ROM data area) being program or erasing: 0=writing protect, 1=enable program and erase
#define bLDO3V3_OFF 0x02 // disable 5V->3.3V LDO: 0=enable LDO for USB and internal oscillator under 5V power, 1=disable LDO, V33 pin input external 3.3V power
#define bWDOG_EN 0x01 // enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow
/* Clock and Sleep and Power Registers */
sfrPCON=0x87;// power control and reset flag
#define SMOD 0x80 // baud rate selection for UART0 mode 1/2/3: 0=slow(Fsys/128 @mode2, TF1/32 @mode1/3, no effect for TF2),
// 1=fast(Fsys/32 @mode2, TF1/16 @mode1/3, no effect for TF2)
#define bRST_FLAG1 0x20 // ReadOnly: recent reset flag high bit
#define bRST_FLAG0 0x10 // ReadOnly: recent reset flag low bit
#define MASK_RST_FLAG 0x30 // ReadOnly: bit mask of recent reset flag
#define RST_FLAG_SW 0x00
#define RST_FLAG_POR 0x10
#define RST_FLAG_WDOG 0x20
#define RST_FLAG_PIN 0x30
// bPC_RST_FLAG1 & bPC_RST_FLAG0: recent reset flag
// 00 - software reset, by bSW_RESET=1 @(bBOOT_LOAD=0 or bWDOG_EN=1)
// 01 - power on reset
// 10 - watch-dog timer overflow reset
// 11 - external input manual reset by RST pin
#define GF1 0x08 // general purpose flag bit 1
#define GF0 0x04 // general purpose flag bit 0
#define PD 0x02 // power-down enable bit, auto clear by wake-up hardware
sfrCLOCK_CFG=0xB9;// system clock config: lower 3 bits for system clock Fsys, Write@SafeMode
#define bOSC_EN_XT 0x40 // external oscillator enable, need quartz crystal or ceramic resonator between XI and XO pins
#define bWDOG_IF_TO 0x20 // ReadOnly: watch-dog timer overflow interrupt flag, cleared by reload watch-dog count or auto cleared when MCU enter interrupt routine
//sfr ROM_STATUS = 0x86; // ReadOnly: flash-ROM status
#define ROM_STATUS ROM_CTRL
#define bROM_ADDR_OK 0x40 // ReadOnly: flash-ROM writing operation address valid flag, can be reviewed before or after operation: 0=invalid parameter, 1=address valid
// 0 0: float input only, without pullup resistance
// 0 1: push-pull output, strong driving high level and low level
// 1 0: open-drain output and input without pullup resistance
// 1 1: quasi-bidirectional (standard 8051 mode), open-drain output and input with pullup resistance, just driving high level strongly for 2 clocks if turning output level from low to high
#define bSCK 0x80 // serial clock for SPI0
#define bTXD1 0x80 // TXD output for UART1
#define bMISO 0x40 // master serial data input or slave serial data output for SPI0
#define bRXD1 0x40 // RXD input for UART1
#define bMOSI 0x20 // master serial data output or slave serial data input for SPI0
#define bPWM1 0x20 // PWM output for PWM1
#define bUCC2 0x20 // CC2 for USB type-C
#define bAIN2 0x20 // AIN2 for ADC
#define bT2_ 0x10 // alternate pin for T2
#define bCAP1_ 0x10 // alternate pin for CAP1
#define bSCS 0x10 // slave chip-selection input for SPI0
#define bUCC1 0x10 // CC1 for USB type-C
#define bAIN1 0x10 // AIN1 for ADC
#define bTXD_ 0x08 // alternate pin for TXD of UART0
#define bRXD_ 0x04 // alternate pin for RXD of UART0
#define bT1_GATE 0x80 // gate control of timer1: 0=timer1 run enable while TR1=1, 1=timer1 run enable while P3.3 (INT1) pin is high and TR1=1
#define bT1_CT 0x40 // counter or timer mode selection for timer1: 0=timer, use internal clock, 1=counter, use P3.5 (T1) pin falling edge as clock
#define bT1_M1 0x20 // timer1 mode high bit
#define bT1_M0 0x10 // timer1 mode low bit
#define MASK_T1_MOD 0x30 // bit mask of timer1 mode
// bT1_M1 & bT1_M0: timer1 mode
// 00: mode 0, 13-bit timer or counter by cascaded TH1 and lower 5 bits of TL1, the upper 3 bits of TL1 are ignored
// 01: mode 1, 16-bit timer or counter by cascaded TH1 and TL1
// 10: mode 2, TL1 operates as 8-bit timer or counter, and TH1 provide initial value for TL1 auto-reload
// 11: mode 3, stop timer1
#define bT0_GATE 0x08 // gate control of timer0: 0=timer0 run enable while TR0=1, 1=timer0 run enable while P3.2 (INT0) pin is high and TR0=1
#define bT0_CT 0x04 // counter or timer mode selection for timer0: 0=timer, use internal clock, 1=counter, use P3.4 (T0) pin falling edge as clock
#define bT0_M1 0x02 // timer0 mode high bit
#define bT0_M0 0x01 // timer0 mode low bit
#define MASK_T0_MOD 0x03 // bit mask of timer0 mode
// bT0_M1 & bT0_M0: timer0 mode
// 00: mode 0, 13-bit timer or counter by cascaded TH0 and lower 5 bits of TL0, the upper 3 bits of TL0 are ignored
// 01: mode 1, 16-bit timer or counter by cascaded TH0 and TL0
// 10: mode 2, TL0 operates as 8-bit timer or counter, and TH0 provide initial value for TL0 auto-reload
// 11: mode 3, TL0 is 8-bit timer or counter controlled by standard timer0 bits, TH0 is 8-bit timer using TF1 and controlled by TR1, timer1 run enable if it is not mode 3
sfrTL0=0x8A;// low byte of timer 0 count
sfrTL1=0x8B;// low byte of timer 1 count
sfrTH0=0x8C;// high byte of timer 0 count
sfrTH1=0x8D;// high byte of timer 1 count
/* UART0 Registers */
sfrSCON=0x98;// UART0 control (serial port control)
sbitSM0=SCON^7;// UART0 mode bit0, selection data bit: 0=8 bits data, 1=9 bits data
sbitEXEN2=T2CON^3;// enable T2EX trigger function: 0=ignore T2EX, 1=trigger reload or capture by T2EX edge
sbitTR2=T2CON^2;// timer2 run enable
sbitC_T2=T2CON^1;// timer2 clock source selection: 0=timer base internal clock, 1=external edge counter base T2 falling edge
sbitCP_RL2=T2CON^0;// timer2 function selection (force 0 if RCLK=1 or TCLK=1): 0=timer and auto reload if count overflow or T2EX edge, 1=capture by T2EX edge
sfrT2MOD=0xC9;// timer 2 mode and timer 0/1/2 clock mode
#define bTMR_CLK 0x80 // fastest internal clock mode for timer 0/1/2 under faster clock mode: 0=use divided clock, 1=use original Fsys as clock without dividing
#define bT2_CLK 0x40 // timer2 internal clock frequency selection: 0=standard clock, Fsys/12 for timer mode, Fsys/4 for UART0 clock mode,
// 1=faster clock, Fsys/4 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for timer mode, Fsys/2 @bTMR_CLK=0 or Fsys @bTMR_CLK=1 for UART0 clock mode
#define bT1_CLK 0x20 // timer1 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1
#define bT0_CLK 0x10 // timer0 internal clock frequency selection: 0=standard clock, Fsys/12, 1=faster clock, Fsys/4 if bTMR_CLK=0 or Fsys if bTMR_CLK=1
#define bT2_CAP_M1 0x08 // timer2 capture mode high bit
#define bT2_CAP_M0 0x04 // timer2 capture mode low bit
// bT2_CAP_M1 & bT2_CAP_M0: timer2 capture point selection
// x0: from falling edge to falling edge
// 01: from any edge to any edge (level changing)
// 11: from rising edge to rising edge
#define T2OE 0x02 // enable timer2 generated clock output: 0=disable output, 1=enable clock output at T2 pin, frequency = TF2/2
#define bT2_CAP1_EN 0x01 // enable T2 trigger function for capture 1 of timer2 if RCLK=0 & TCLK=0 & CP_RL2=1 & C_T2=0 & T2OE=0
sfrRCAP2L=0xCA;// low byte of reload & capture value
sfrRCAP2H=0xCB;// high byte of reload & capture value
sfr16T2COUNT=0xCC;// counter, little-endian
sfrTL2=0xCC;// low byte of timer 2 count
sfrTH2=0xCD;// high byte of timer 2 count
sfr16T2CAP1=0xCE;// ReadOnly: capture 1 value for timer2
sfrT2CAP1L=0xCE;// ReadOnly: capture 1 value low byte for timer2
sfrT2CAP1H=0xCF;// ReadOnly: capture 1 value high byte for timer2
/* PWM1/2 Registers */
sfrPWM_DATA2=0x9B;// PWM data for PWM2
sfrPWM_DATA1=0x9C;// PWM data for PWM1
sfrPWM_CTRL=0x9D;// PWM 1/2 control
#define bPWM_IE_END 0x80 // enable interrupt for PWM mode cycle end
#define bPWM2_POLAR 0x40 // PWM2 output polarity: 0=default low and high action, 1=default high and low action
#define bPWM1_POLAR 0x20 // PWM1 output polarity: 0=default low and high action, 1=default high and low action
#define bPWM_IF_END 0x10 // interrupt flag for cycle end, write 1 to clear or write PWM_CYCLE or load new data to clear
#define bPWM2_OUT_EN 0x08 // PWM2 output enable
#define bPWM1_OUT_EN 0x04 // PWM1 output enable
#define bPWM_CLR_ALL 0x02 // force clear FIFO and count of PWM1/2
sfrPWM_CK_SE=0x9E;// clock divisor setting
/* SPI0/Master0/Slave Registers */
sfrSPI0_STAT=0xF8;// SPI 0 status
sbitS0_FST_ACT=SPI0_STAT^7;// ReadOnly: indicate first byte received status for SPI0
sbitS0_IF_OV=SPI0_STAT^6;// interrupt flag for slave mode FIFO overflow, direct bit address clear or write 1 to clear
sbitS0_IF_FIRST=SPI0_STAT^5;// interrupt flag for first byte received, direct bit address clear or write 1 to clear
sbitS0_IF_BYTE=SPI0_STAT^4;// interrupt flag for a byte data exchanged, direct bit address clear or write 1 to clear or accessing FIFO to clear if bS0_AUTO_IF=1
sbitS0_FREE=SPI0_STAT^3;// ReadOnly: SPI0 free status
sbitS0_T_FIFO=SPI0_STAT^2;// ReadOnly: tx FIFO count for SPI0
sbitS0_R_FIFO=SPI0_STAT^0;// ReadOnly: rx FIFO count for SPI0
sfrSPI0_DATA=0xF9;// FIFO data port: reading for receiving, writing for transmittal
#define bADC_EN 0x08 // control ADC power: 0=shut down ADC, 1=enable power for ADC
#define bCMP_EN 0x04 // control comparator power: 0=shut down comparator, 1=enable power for comparator
#define bADC_CLK 0x01 // ADC clock frequency selection: 0=slow clock, 384 Fosc cycles for each ADC, 1=fast clock, 96 Fosc cycles for each ADC
sfrADC_DATA=0x9F;// ReadOnly: ADC data
/* Touch-key timer Registers */
sfrTKEY_CTRL=0xC3;// touch-key control
#define bTKC_IF 0x80 // ReadOnly: interrupt flag for touch-key timer, cleared by writing touch-key control or auto cleared when start touch-key checking
sbitU_IS_NAK=USB_INT_FG^7;// ReadOnly: indicate current USB transfer is NAK received
sbitU_TOG_OK=USB_INT_FG^6;// ReadOnly: indicate current USB transfer toggle is OK
sbitU_SIE_FREE=USB_INT_FG^5;// ReadOnly: indicate USB SIE free status
sbitUIF_FIFO_OV=USB_INT_FG^4;// FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
sbitUIF_HST_SOF=USB_INT_FG^3;// host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
sbitUIF_SUSPEND=USB_INT_FG^2;// USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
sbitUIF_TRANSFER=USB_INT_FG^1;// USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
sbitUIF_DETECT=USB_INT_FG^0;// device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
sbitUIF_BUS_RST=USB_INT_FG^0;// bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
sfrUSB_INT_ST=0xD9;// ReadOnly: USB interrupt status
#define bUIS_IS_NAK 0x80 // ReadOnly: indicate current USB transfer is NAK received for USB device mode
#define bUIS_TOG_OK 0x40 // ReadOnly: indicate current USB transfer toggle is OK
#define bUIS_TOKEN1 0x20 // ReadOnly: current token PID code bit 1 received for USB device mode
#define bUIS_TOKEN0 0x10 // ReadOnly: current token PID code bit 0 received for USB device mode
#define MASK_UIS_TOKEN 0x30 // ReadOnly: bit mask of current token PID code received for USB device mode
#define UIS_TOKEN_OUT 0x00
#define UIS_TOKEN_SOF 0x10
#define UIS_TOKEN_IN 0x20
#define UIS_TOKEN_SETUP 0x30
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
// 00: OUT token PID received
// 01: SOF token PID received
// 10: IN token PID received
// 11: SETUP token PID received
#define MASK_UIS_ENDP 0x0F // ReadOnly: bit mask of current transfer endpoint number for USB device mode
#define MASK_UIS_H_RES 0x0F // ReadOnly: bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
sfrUSB_MIS_ST=0xDA;// ReadOnly: USB miscellaneous status
#define bUMS_SOF_PRES 0x80 // ReadOnly: indicate host SOF timer presage status
#define bUMS_SOF_ACT 0x40 // ReadOnly: indicate host SOF timer action status for USB host
#define bUMS_SIE_FREE 0x20 // ReadOnly: indicate USB SIE free status
#define bUMS_R_FIFO_RDY 0x10 // ReadOnly: indicate USB receiving FIFO ready status (not empty)
#define bUMS_BUS_RESET 0x08 // ReadOnly: indicate USB bus reset status
#define bUMS_SUSPEND 0x04 // ReadOnly: indicate USB suspend status
#define bUMS_DM_LEVEL 0x02 // ReadOnly: indicate UDM level saved at device attached to USB host
#define bUMS_DEV_ATTACH 0x01 // ReadOnly: indicate device attached status on USB host
sfrUSB_RX_LEN=0xDB;// ReadOnly: USB receiving length
#define bUC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable
#define bUC_SYS_CTRL1 0x20 // USB system control high bit
#define bUC_SYS_CTRL0 0x10 // USB system control low bit
#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control
// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control
// 0 00: disable USB device and disable internal pullup resistance
// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
// 0 1x: enable USB device and enable internal pullup resistance
// 1 00: enable USB host and normal status
// 1 01: enable USB host and force UDP/UDM output SE0 state
// 1 10: enable USB host and force UDP/UDM output J state
// 1 11: enable USB host and force UDP/UDM output resume or K state
#define bUC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
#define bUC_RESET_SIE 0x04 // force reset USB SIE, need software clear
#define bUC_CLR_ALL 0x02 // force clear FIFO and count of USB
#define bUC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB
sfrUSB_DEV_AD=0xE3;// USB device address, lower 7 bits for USB device address
#define bUDA_GP_BIT 0x80 // general purpose bit
#define MASK_USB_ADDR 0x7F // bit mask for USB device address
sfrUEP1_DMA_H=0xEF;// endpoint 1 buffer start address high byte
//sfr UH_SETUP = 0xD2; // host aux setup
#define UH_SETUP UEP1_CTRL
#define bUH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub
#define bUH_SOF_EN 0x40 // USB host automatic SOF enable
//sfr UH_RX_CTRL = 0xD4; // host receiver endpoint control
#define UH_RX_CTRL UEP2_CTRL
#define bUH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
#define bUH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define bUH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
//sfr UH_EP_PID = 0xD5; // host endpoint and token PID, lower 4 bits for endpoint number, upper 4 bits for token PID
#define UH_EP_PID UEP2_T_LEN
#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer
#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer
//sfr UH_TX_CTRL = 0xD6; // host transmittal endpoint control
#define UH_TX_CTRL UEP3_CTRL
#define bUH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
#define bUH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define bUH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
